Dry Etching Step Research Articles

Monocrystalline silicon carbide nanoelectromechanical systems

SiC is an extremely promising material for nanoelectromechanical systems given its large Young's modulus and robust surface properties. We have patterned nanometer scale electromechanical resonators from single-crystal 3C-SiC layers grown epitaxially upon Si substrates. A surface nanomachining process is described that involves electron beam lithography followed by dry anisotropic and selective electron cyclotron resonance plasma etching steps. Measurements on a representative family of the resulting devices demonstrate that, for a given geometry, nanometer-scale SiC resonators are capable of yielding substantially higher frequencies than GaAs and Si resonators.

Laminated, sacrificial-poly MEMS technology in standard CMOS

We present a micro-machining technology which enables MEMS fabrication on standard CMOS with very dense electrical/mechanical integration. Micro-mechanical structures are fabricated alongside circuits on standard 0.5-μm 3-metal CMOS dice using four maskless dry-etch steps. The resulting laminated beams are made of CMOS metal and dielectric layers. Multi-conductor mechanical structures can carry multiple signals for actuation and sensing. Narrow vertical and lateral gaps enable efficient XYZ electrostatic actuation and fine capacitive position sensing. Experiments show that mechanical structures can be integrated 1.5 μm away from signal-processing circuits, resulting in very low parasitics, good system performance, and small die size.

Low-frequency noise properties of selectively dry etched InP HEMT's

The low-frequency noise of lattice-matched InAlAs/InGaAs/InP high electron mobility transistors (HEMT's) gate recess etched with a highly selective dry etching process and with conventional wet etching were studied at different gate and drain biases for the temperature range of 77-340 K. The measurements showed a significantly lower normalized drain current 1/f noise for the dry etched HEMT's under all bias conditions. No difference in the normalized gate current 1/f noise could be observed for the two device types. By varying the temperature, four electron traps could be identified in the drain current noise spectra for both dry and wet etched devices. No additional traps were introduced by the dry etching step. The concentration of the main trap in the Schottky layer is one order of magnitude lower for the dry etched HEMT's. No hydrogen passivation of the shallow donors was observed in these devices. We presume hydrogen passivation of the deep levels as the cause for the trap density reduction. The kink effect in the dry etched HEMT's was observed to be reduced significantly compared with wet etched devices which gives further evidence of trap passivation during dry etching. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of devices for noise sensitive applications.

Recessed gate GaN field effect transistor

A n + n GaN metal semiconductor field effect transistor was fabricated, with the gate recess formed by Electron Cyclotron Resonance BCl 3N 2 dry etching. The drain source breakdown voltage is > 20 V, and annealing at 400°C was found to be necessary after the dry etch step to produce a high gate breakdown voltage (∼ 25 V).

An investigation of various post-RIE cleaning processes for dry etched InP-based HEMTs

Post-RIE cleaning processes after the dry gate recess etching step of lattice-matched InGaAs/InAlAs/InP-HEMTs using an oxygen plasma treatment of the surface followed by various wet chemical steps have been investigated. The treated surfaces have been analyzed using X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). In addition, the electrical characteristics have been assessed by DC and microwave measurements of HEMT devices. A considerable improvement of the surface quality using post-RIE cleaning has been observed, resulting in better electrical device performance.

Laminated high-aspect-ratio microstructures in a conventional CMOS process

Electrostatically actuated microstructures with high-aspect-ratio laminated-beam suspensions have been fabricated using a 0.8 μm three-metal CMOS process followed by a sequence of three maskless dry-etching steps. Laminated structures are etched of the CMOS silicon oxide, silicon nitride, and aluminum layers. The key to the process is the use of the CMOS metallization as an etch-resistant mask to define the microstructures. A minimum beam width of 1.2 μm, gap of 1.2 μm, and maximum beam thickness of 4.8 μm are obtained. These structural features will scale in size as the CMOS technology improves. The laminated material has an effective Young's modulus of 61 GPa, an effective residual stress of 69 MPa, and a residual strain gradient of 2 × 10 −4 μm −1. Multi-conductor electrostatic micromechanisms, such as self-actuating springs, x−y microstages, and nested comb-drive lateral resonators, are successfully produced. A self-actuating spring is a lateral electrostatic microactuator without a stator that is insensitive to out-of-plane curl. A spring 107 μm wide by 109 μm long excited by an 11 V a.c. signal has a measured resonance amplitude of 1 μm at 14.9 kHz. Finite-element simulation using the extracted value of Young's modulus predicts the resonance frequencies of the springs to within 7% of the measured values.

Released Si microstructures fabricated by deep etching and shallow diffusion

A novel etch-diffusion process is developed for fabricating high-aspect-ratio Si structures for microsensors. This is accomplished by first dry etching narrow gap Si microstructures using an electron cyclotron resonance (ECR) source, followed by a shallow B diffusion to fully convert the etched microstructures to p/sup ++/ layer. Microstructures up to 40 /spl mu/m deep with 2-/spl mu/m-wide gaps were etched with a Cl/sub 2/ plasma generated using the ECR source. Vertical profile and smooth morphology were obtained at low pressure. A shallow B diffusion at 1175/spl deg/C for 5.5 h. was then carried out to convert the 40-/spl mu/m-thick resonant elements to p/sup ++/ layer. A second dry etching step was used to remove the thin p/sup ++/ layer around the bottom of the resonant elements, followed by bonding to glass and selective wet etch. Released high-aspect-ratio Si microsensors with thicknesses of 35 /spl mu/m have been demonstrated. At atmospheric pressure, only 5 V/sub dc/ driving voltage is needed for 2.5 /spl mu/m vibration amplitude, which is less than the 10 V/sub dc/ required to drive 12-/spl mu/m-thick resonators fabricated by conventional dissolved wafer process.

Fabrication of photonic band-gap crystals

We describe the fabrication of three-dimensional photonic crystals using a reproducible and reliable procedure consisting of electron beam lithography followed by a sequence of dry etching steps. Careful fabrication has enabled us to define photonic crystals with 280 nm holes defined with 350 nm center to center spacings in GaAsP and GaAs epilayers. We construct these photonic crystals by transferring a submicron pattern of holes from 70-nm-thick polymethylmethacrylate resist layers into 300-nm-thick silicon dioxide ion etch masks, and then anisotropically angle etching the III-V semiconductor material using this mask. Here, we show the procedure used to generate photonic crystals with up to four lattice periods depth.

Molybdenum silicide based attenuated phase-shift masks

The use of phase shifting masks (PSMs) causes revolutionary improvements of the performance of existing wafer steppers. Nowadays the attenuated PSM, also referred to as halftone, is found to be most attractive, as the technique is self-aligned. Moreover, the number of additional process steps in mask fabrication is limited to a dry etching step. Typically, both focus and exposure latitudes for contact holes of 0.35 μm are improved by a factor of 1.5–2 over a conventional mask. As linewidths on mask shrink towards 1 μm (a critical dimension of 0.25 μm, at 4× magnification) and below, the required critical dimension control becomes much tighter. It becomes more and more clear that the accuracy cannot be met anymore with wet etching of chrome. Sputtered molybdenum silicide (MoSi) is easier to dry etch than chrome and is therefore an important candidate as alternative opaque material on masks. The use of MoSi for attenuated PSMs is discussed. This approach has the advantage over the use of an SOG/Cr combination in that only a single dry etch process is required to etch the stack, since both materials can be etched using fluorine based plasmas. This is in contrast to chrome/shifter attenuated masks where chrome and shifter are etched separately, either wet/dry or both dry but in different chemistries. Recently published work describes the application of a single layer of a MoSiO or MoSiON with the required opacity and phase shift, by careful tuning of the refractive index and extinction coefficient. A comparison to these so-called embedded PSMs is included. For the latter an important disadvantage is the lack of conductivity of the layer, such that an extra (sacrificial) layer is required for charge dissipation during electron-beam exposure. An intermediate solution, referred to as partially embedded, is suggested as a compromise.

Temperature Effects in the Dry Etching Step of a Silylation Process

Substrate temperature is generally considered as an important parameter in polymer plasma etching. In this study, we demonstrate that if the substrate is not efficiently cooled during the dry development step of silylated resists, the silylated area may be melted and can flow on the resist pattern. This phenomenon is attributed to the low glass transition temperature of the silylated area.

Reduction of sidewall roughness during dry etching of SiO2

The appearance of striations on dry etched semiconductor laser mesas is a common feature of these structures. We describe a number of different methods of reducing the extent of this roughness, including the choice of dielectric etch chemistry, modification of the initial resist processing, and deposition of a SiN sidewall to prevent additional roughening during the plasma etch step. SF6 is found to be preferable to CF4 for dielectric etching because of an absence of polymer formation. This produces smoother SiO2 sidewalls. Flood exposure of theinitial photoresist mask and optimization of the postbake temperature also produces smoother sidewalls on the subsequently etched SiO2. The sidewall can also be protected from roughening that occurs during the dry etch step by coating it with a low temperature SiN layer. A combination of all of these methods produces sidewalls with morphological variations of ≤500 Å.

Reduction of Sidewall Roughness During Dry Etching of SiO2

The appearance of striations on dry etched semiconductor laser mesas is a common feature of these structures. We describe a number of different methods of reducing the extent of this roughness, including the choice of dielectric etch chemistry, modification of the initial resist processing and deposition of a SiN sidewall to prevent additional rougheningduring the plasma etch step. SF6 is found to be preferable to CF4 for dielectric etching because of an absence of polymer formation. This produces smoother SiO2 sidewalls. Flood exposure of the initial photoresist mask and optimization of the postbake temperature also produces smoomer sidewalls on the subsequently etched SiO2. The sidewall can also be protected from roughening that occurs during the dry etch step by coating it with a low temperature SiN layer. A combination of all of these methods produces sidewalls with morphological variations of ≤500Å.

Dry etch processing of GaAs/AlGaAs high electron mobility transistor structures

Damage introduction into GaAs/AlGaAs high electron mobility transistor (HEMT) structures during either pattern transfer or gate mesa etching steps has been characterized. For O2 reactive ion etching of the polydimethylglutarimide (PMGI) planarizing layer in a trilevel resist mask, the threshold dc bias for observable damage introduction in the AlGaAs donor layer is ∼200 V. This threshold bias for damage is a function of the PMGI overetch time and for extended times (>10 min), a decrease in saturated drain-source current (IDSS) of the HEMTs can be detected for oxygen ions accelerated through a bias of ∼150 V. The use of combined electron cyclotron resonance (ECR)/radio frequency (rf) O2 discharges enhances the PMGI etch rate without creating additional damage to the device, and 0.25-μm gate widths have been demonstrated. Gate mesa formation by etching the GaAs cap with CCl2F2/O2 or CH4/H2/Ar discharges is shown to produce damage in the underlying AlGaAs at dc negative biases of 125–150 V. In addition, substantial hydrogen passivation of the Si dopants occurs for the latter mixture. Recovery of the initial carrier concentration in the damaged HEMT occurs around 400 °C, provided the maximum dc biases were kept to ≤400 V during the dry etch step. Finally, changes in the surface chemistry of the exposed AlGaAs after various post-RIE processing steps have been monitored by x-ray photoelectron spectroscopy. Complete removal of AlF3 was obtained only after careful H2O and NH4OH:H2O rinsing, while chlorides are removed by H2O alone.

Benign Precursors for Semiconductor Processing

Semiconductor manufacture not only requires efficient processes that produce reliable products, but also should use benign precursors as input materials to generate a product and by-products that are environmentally safe. Current device processing, by its nature, is demanding and depends on difficult-to-handle materials. As part of a long-term strategy to develop safer, more efficient processes that also have zero environmental impact, a technique is reported here for III-V processing that obviates the need for transport, storage, and handling of arsine in high-pressure cylinders. This technique, called in situ generation, provides an immediate solution for a potential safety problem in current semiconductor processing, the “sudden release hazard” of cylinders of compressed toxic gases. Other promising solutions for economically viable processing that meet safety and environmental compliances exploit chemically inert reagents in plasma reactors or use nontoxic precursors. Applications are described for the fabrication of a broad range of devices requiring dry etching and chemical vapor deposition processing steps.

Influence of Two‐Level Planar Interconnection Processes Using Bias‐Sputtered SiO2 for MOSFETs

The influence of two‐level planar interconnection using bias‐sputtered for MOSFETs has been investigated. The degradation of static characteristics due to both the deposition and two‐level interconnection was small, and was reduced to a negligibly small amount by annealing at 450°C in a ambient for 30 min. However, the influence on long‐term reliability, i.e., hot‐carrier immunity, was not negligible and could not be removed by annealing. The origins of the long‐term reliability degradation in the two‐level planar interconnection were attributed to, primarily, the bias sputter deposition step and, secondarily, the dry etching step for via holes. It was possible to reduce the degradation due to the bias sputter deposition step to the same degree as that of the via hole dry etching step by raising the deposition temperature.

A New Self-Aligned Framed Mask Method for Selective Oxidation

A new selective oxidation method, which realizes fine isolation width for MOS LSIs, has been developed. The oxidation mask in this method has a Si3N4 frame formed at a perimeter of a conventional mask pattern by self-aligned technique. This technique is composed of deposition step of Si3N4 film to cover the conventional mask and dry etching step of this film to form the frame without a photoresist pattern. Bird's beak extent is suppressed to less than 300 nm. Dislocation generation in silicon substrate is also suppressed in this framed mask method. Bird's beak suppression brings about extention in an effective device area and realizes a transistor with effective channel width 1.0 µm wider than that in the conventional mask method. The p-n junction prepared by this new method exhibits as small leakage current as that by the conventional method.