Abstract
The influence of two‐level planar interconnection using bias‐sputtered for MOSFETs has been investigated. The degradation of static characteristics due to both the deposition and two‐level interconnection was small, and was reduced to a negligibly small amount by annealing at 450°C in a ambient for 30 min. However, the influence on long‐term reliability, i.e., hot‐carrier immunity, was not negligible and could not be removed by annealing. The origins of the long‐term reliability degradation in the two‐level planar interconnection were attributed to, primarily, the bias sputter deposition step and, secondarily, the dry etching step for via holes. It was possible to reduce the degradation due to the bias sputter deposition step to the same degree as that of the via hole dry etching step by raising the deposition temperature.
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