DRAM Chips Research Articles

OPERATING SYSTEMS TECHNIQUES FOR PARALLEL COMPUTATION IN INTELLIGENT MEMORY

Advances in DRAM density have led to several proposals to perform computation in memory [1] [2] [3]. Active Pages is a page-based model of intelligent memory that can exploit large amounts of parallel computation in data-intensive applications. With a simple VLIW processor embedded near each page on DRAM, Active Page memory systems achieve up to 1000X speedups over conventional memory systems [4]. Active Pages are specifically designed to support virtualized hardware resources. In this study, we examine operating system techniques that allow Active Page memories to share, or multiplex, embedded VLIW processors across multiple physical Active Pages. We explore the trade-off between individual page-processor performance and page-level multiplexing. We find that hardware costs of computational logic can be reduced from 31% of DRAM chip area to 12%, through multiplexing, without significant loss in performance. Furthermore, manufacturing defects that disable up to 50% of the page processors can be tolerated through efficient resource allocation and associative multiplexing.

Using a user-level memory thread for correlation prefetching

This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: the correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide usability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.

Signal integrity and design consideration of an MCM for video graphic acceleration

This paper introduces a cost effective multichip module (MCM) for video graphic acceleration (VGA) of portable computers. A 1.7 million gate graphic processor IC and two 8 M byte DRAM chips have been integrated into a 31/spl times/31 mm/sup 2/ 4-layer PBGA. Signal integrity measurement and analysis has been performed to optimize performance of the present design and a direction for improvement for the next generation product. This study confirms that more consideration given to the MCM application at the IC design stage will maximize MCM performance.

Cached DRAM for ILP processor memory access latency reduction

Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced DRAM techniques for reducing memory access latency in instruction-level-parallelism processors.

High-performance DRAMs in workstation environments

This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (/spl sim/10, as opposed to /spl sim/1 or /spl sim/100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Double Data Rate, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: 1) Current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; 2) bus transmission speed will soon become a primary factor limiting memory-system performance; 3) the post-L2 address stream still contains significant locality, though it varies from application to application; 4) systems without L2 caches are feasible for low- and medium-speed CPUs (1 GHz and below); and 5) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time.

Memory access scheduling

The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth.

A performance comparison of contemporary DRAM architectures

In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study of a representative group, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use on the order of 10 DRAM chips. The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: (a) current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; (b) bus transmission speed will soon become a primary factor limiting memory-system performance; (c) the post-L2 address stream still contains significant locality, though it varies from application to application; and (d) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time.

Scanning Auger microscopy study of electromigration induced failure in submicrometric microelectronic devices

Scanning Auger microscopy is a powerful tool to investigate elemental and chemical composition of surfaces, interfaces and thin films. Thanks to its high lateral resolution (better than 10 nm at 20 keV using the last generation of Schottky field emission tip) and to the surface sensitivity of the Auger electrons (between 5 and 30 Å, depending on the investigated element), it is very useful in microelectronics laboratories, where the size of the components is often less than 200 nm. In this work we shall present the analysis performed by means of a scanning Auger microscope on the elemental and chemical distribution on a defective submicrometric via contact (about 200×500 nm) connecting two metal lines of a 64 Mb DRAM chip before and after an extreme electric test, in order to study the effect of a huge current passing through the contact. The analysis has been performed with very high spatial resolution (better than 20 nm) onto samples that showed different electrical behaviour after the test. Our measurements have allowed us to describe the bad behaviour of the circuit due to a migration of some metal atoms induced by electron flow.

A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits

The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences of hot-carrier effects on gate capacitance variation and its impact on the mismatch drift of MOS dynamic circuits. It is shown here that the impact of hot-carrier-induced gate capacitance variation on VLSI circuits is more critical than DC parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64 Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carrier stress.

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process.

Pion-induced soft upsets in 16 mbit DRAM chips

Measurements of the soft upset cross section due to energetic charged pions were made in various 16 Mbit memory chips, as a function of incident pion energy and for chips with different cell technologies. Significant differences are seen to exist between cell technologies, up to a factor of 1000 in cross section. Upset cross sections are reported that exhibit proportionality to the reaction cross section for pions on silicon, including the well-known enhancement over proton and neutron cross sections near the delta resonance. Implications of this enhancement for pion-induced upsets due to cosmic ray fluxes are discussed.

Limitations and challenges of multigigabit DRAM chip design

This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V/sub T/) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V/sub T/, dynamic V/sub T/, and node-boosting schemes.

Low-voltage, high-speed circuit designs for gigabit DRAMs

This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-/spl mu/m twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t/sub RAC/) of 28 ns at V/sub cc/=1.5 V and T=25/spl deg/C has been obtained.

Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period.

A case for intelligent RAM

Two trends call into question the current practice of fabricating microprocessors and DRAMs as different chips on different fabrication lines. The gap between processor and DRAM speed is growing at 50% per year; and the size and organization of memory on a single DRAM chip is becoming awkward to use, yet size is growing at 60% per year. Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, and improve energy efficiency. It also allows more flexible selection of memory size and organization, and promises savings in board area. This article reviews the state of microprocessors and DRAMs today, explores some of the opportunities and challenges for IRAMs, and finally estimates performance and energy efficiency of three IRAM designs.

Built-in self-test for folded bit-line Mbit DRAMs

In this paper an efficient and comprehensive algorithm for deriving near optimal parallel tests for neighborhood pattern sensitive faults (NPSFs) detection for an arbitrary type of neighborhood is presented. When k is odd (even) it is based on the decomposition of a directed (undirected) k-cube into a minimal number of edge-disjoint tours. The approach considerably simplifies test-pattern generator (TPG) requirements and makes it suitable for implementation on a VLSI chip. The proposed algorithm is utilized to derive a parallel self-test for detection of unidirectional NPSFs in solded bit-line Mbit DRAM chips. An integrated test strategy covers the most typical functional and parametric faults by execution of retention and marginal tests during the parallel test for unidirectional NPSFs detection. Results showed an improved test coverage of k-coupling faults by approximately 10–65% compared to “tiling” method when k varies from 2 to 9. The total chip area expansion is less than 0.5% for Mbit DRAMs. A test length is 1072 N w when a lower bound is 1024 N w, where N w is the number of word-lines. Thus 64 MBit DRAM {8192 × 8192} is tested within a second when the speed of the test clock is 10 MHz.

A sense and restore technique for multilevel DRAM

A technique for storing and retrieving 2 b of data encoded as 4 voltage levels in a single DRAM memory cell is described. The 4 data levels and sense amplifier reference levels are created through simple charge redistribution techniques on local bitlines. Memory cells, sense amplifiers, and wordline drivers identical to standard DRAM are employed. A SPICE simulation using a representative 16 M DRAM process model shows correct sense and restore operation, with accurate generation of reference levels. The capacity of DRAM chips can be doubled with the addition of multilevel support circuitry that occupies less than 20% of die area.

A 286 mm/sup 2/ 256 Mb DRAM with ×32 both-ends DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to /spl times/32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 /spl mu/m CMOS technology. The chip measures 13.25 mm/spl times/21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85/spl deg/C. In addition, a 100 MHz/spl times/32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated.

A parallel processing chip with embedded DRAM macros

A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7/spl times/14.7 mm/sup 2/ die. The DRAM design is based on a 32-K/spl times/9-b (288-Kb) self-consistent macro form. It has independent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements. The logic part of the chip consists of eight 16-b CPUs and some broadcast logic circuits. Each CPU and two DRAM macros (64-KB) comprise a processing element (PE), and hypercube connections among eight PE's are made for the scalable MPP capability. Each chip delivers 50-MIPS of performance at 2.7 W.

SIMULTANEOUS SWITCHING NOISE ANALYSIS OF A 16 MB × 9 DRAM SIMM MEMORY MODULE

HSPICE simulations have been performed for a 16 Mb×9 SIMM memory module and the simultaneous switching noise has been investigated. The SPICE model of the SIMM memory module is made up of a PCB circuit model and a simplified DRAM chip model. To keep the SPICE simulation time within reasonable bounds, a simplified circuit model of a 16 Mb DRAM chip was generated by keeping the basic physical DRAM structure in the model including the bit-line sense amplifiers. The parameter values of the circuit elements in the simplified DRAM chip model were tuned to fit the measured transient supply current waveform of a commercial 16 Mb DRAM chip. The SIMM module was placed on a fabricated motherboard PCB and the simultaneous switching noise voltage on the motherboard VSS plane was measured. Good agreement between measurements and HSPICE simulations were observed.