DRAM Chips Research Articles

An Approach for Adaptive DRAM Temperature and Power Management

High-performance DRAMs are providing increasing memory access bandwidth to processors, which is leading to high power consumption and operating temperature in DRAM chips. In this paper, we propose a customized low-power technique for high-performance DRAM systems to improve DRAM page hit rate by buffering write operations that may incur page misses. This approach reduces DRAM system power consumption and temperature without any performance penalty. We combine the throughput-aware page-hit-aware write buffer (TAP) with low-power-state-based techniques for further power and temperature reduction, namely, TAP-low. Our experiments show that a system with TAP-low could reduce the total DRAM power consumption by up to 68.6% (19.9% on average). The steady-state temperature can be reduced by as much as 7.84°C and 2.55°C on average across eight representative workloads.

Virtualized and flexible ECC for main memory

We present a general scheme for virtualizing main memory error-correction mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We rely on this basic idea, which increases flexibility to increase error protection capabilities, improve power efficiency, and reduce system cost; with only small performance overheads. We augment the virtual memory system architecture to detach the physical mapping of data from the physical mapping of its associated ECC information. We then use this mechanism to develop two-tiered error protection techniques that separate the process of detecting errors from the rare need to also correct errors, and thus save energy. We describe how to provide strong chipkill and double-chip kill protection using existing DRAM and packaging technology. We show how to maintain access granularity and redundancy overheads, even when using ×8 DRAM chips. We also evaluate error correction for systems that do not use ECC DIMMs. Overall, analysis of demanding SPEC CPU 2006 and PARSEC benchmarks indicates that performance overhead is only 1% with ECC DIMMs and less than 10% using standard Non-ECC DIMM configurations, that DRAM power savings can be as high as 27%, and that the system energy-delay product is improved by 12% on average.

Virtualized and flexible ECC for main memory

We present a general scheme for virtualizing main memory error-correction mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We rely on this basic idea, which increases flexibility to increase error protection capabilities, improve power efficiency, and reduce system cost; with only small performance overheads. We augment the virtual memory system architecture to detach the physical mapping of data from the physical mapping of its associated ECC information. We then use this mechanism to develop two-tiered error protection techniques that separate the process of detecting errors from the rare need to also correct errors, and thus save energy. We describe how to provide strong chipkill and double-chip kill protection using existing DRAM and packaging technology. We show how to maintain access granularity and redundancy overheads, even when using ×8 DRAM chips. We also evaluate error correction for systems that do not use ECC DIMMs. Overall, analysis of demanding SPEC CPU 2006 and PARSEC benchmarks indicates that performance overhead is only 1% with ECC DIMMs and less than 10% using standard Non-ECC DIMM configurations, that DRAM power savings can be as high as 27%, and that the system energy-delay product is improved by 12% on average.

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection and a cyclic redundancy check (CRC) generator for outer-data inner-command architecture. Measurements for bit error rate and jitter performance of the transmitter was performed on an electrical test board which emulates the real memory system's environment. Also, the effect on power noise was analyzed from the DRAM chips with three class values of power decoupling capacitance for the peripheral part. The results show that no additional coding for the differential I/O protection in DRAM, like CRC, is required up to 5.8-Gb/s/pin operation.

Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs

Demand for memory capacity and bandwidth keeps increasing rapidly in modern computer systems, and memory power consumption is becoming a considerable portion of the system power budget. However, the current DDR DIMM standard is not well suited to effectively serve CMP memory requests from both a power and performance perspective. We propose a new memory module called a multicore DIMM, where DRAM chips are grouped into multiple virtual memory devices, each of which has its own data path and receives separate commands. The Multicore DIMM is designed to improve the energy efficiency of memory systems with small impact on system performance. Dividing each memory modules into 4 virtual memory devices brings a simultaneous 22%, 7.6%, and 18% improvement in memory power, IPC, and system energy-delay product respectively on a set of multithreaded applications and consolidated workloads.

Interface optimization for poly silicon/tungsten gates

Novel dual work function (DWF) based transistors featuring low gate resistances are presented. The process discussed enables extremely fast array timings easily and is thus key to fulfilling the performance requirements for high performance DRAM chips. The key enabler of the advanced gate integration scheme and its properties is the understanding of tuning the interface contact resistance. The objective of this work was to systematically investigate the role of the interface between poly-Si and metal of DRAM gate structures focused on electrical data. Contact resistance values, speed and elemental analysis information summarize the main findings of the gate development and furthermore the stable control of the very thin film stack in high volume production.

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logic process based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.

Energy-aware disk scheduling for soft real-time I/O requests

In this work, we develop energy-aware disk scheduling algorithm for soft real-time I/O. Energy consumption is one of the major factors which bar the adoption of hard disk in mobile environment. Heat dissipation of large scale storage system also calls for an energy-aware scheduling technique to further increase the storage density. The basic idea in this work is to properly determine the I/O burst size so that device can be in standby mode between consecutive I/O bursts and that it can satisfy the soft real-time requirement. We develop an elaborate model which incorporates the energy consumption characteristics, overhead of mode transition in determining the appropriate I/O burst size and the respective disk operating schedule. Efficacy of energy-aware disk scheduling algorithm greatly relies on not only disk scheduling algorithm itself but also various operating system and device firmware related concerns. It is crucial that the various operating system level and device level features need to be properly addressed within disk scheduling framework. Our energy-aware disk scheduling algorithm successfully addresses a number of outstanding issues. First, we examine the effect of OS and hard disk firmware level prefetch policy and incorporate its effect in our disk scheduling framework. Second, our energy aware scheduling framework can allocate a certain fraction of disk bandwidth to handle sporadically arriving non real-time I/O's. Third, we examine the relationship between lock granularity of the buffer management and energy consumption. We develop a prototype software with energy-aware scheduling algorithm. In our experiment, proposed algorithm can reduce the energy consumption to one fourth if we use energy-aware disk scheduling algorithm. However, energy-aware disk scheduling algorithm increases buffer requirement significantly, e.g., from 4 to 140 KByte. We carefully argue that the buffer overhead is still justifiable given the cost of DRAM chip and importance of energy management in modern mobile devices. The result of our work not only provides the energy efficient scheduling algorithm but also provides an important guideline in capacity planning of future energy efficient mobile devices.

A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

Feasibility of decoupling memory management from the execution pipeline

In conventional architectures, the central processing unit (CPU) spends a significant amount of execution time allocating and de-allocating memory. Efforts to improve memory management functions using custom allocators have led to only small improvements in performance. In this work, we test the feasibility of decoupling memory management functions from the main processing element to a separate memory management hardware. Such memory management hardware can reside on the same die as the CPU, in a memory controller or embedded within a DRAM chip. Using Simplescalar, we simulated our architecture and investigated the execution performance of various benchmarks selected from SPECInt2000, Olden and other memory intensive application suites. Hardware allocator reduced the execution time of applications by as much as 50%. In fact, the decoupled hardware results in a performance improvement even when we assume that both the hardware and software memory allocators require the same number of cycles. We attribute much of this improved performance to improved cache behavior since decoupling memory management functions reduces cache pollution caused by dynamic memory management software. We anticipate that even higher levels of performance can be achieved by using innovative hardware and software optimizations. We do not show any specific implementation for the memory management hardware. This paper only investigates the potential performance gains that can result from a hardware allocator.

Concordant Memory Design: An Integrated Statistical Design Approach for Multi-Gigabit DRAM

Concordant memory design incorporates fluctuation in device parameters statistically into signal-to-noise ratio analysis in DRAM. In this design, the effective signal voltage of all cells in a chip is calculated, and the failed bit count of the chip is estimated. The proposed design approach gives us a quantitative evaluation of the memory array and assures 1.4-V array operation of 100-nm-1-Gb DRAM. Calculated dependence of the failed bit count on the array voltage is in close agreement with measured data for the 512-Mb DRAM chip.

Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).

New product announcements as market signals: A content analysis in the DRAM chip industry

New-product announcements (NPAs) have considerable effects on competitors in industrial markets. Several studies have shown that the perceived threat caused by an NPA may trigger severe competitive reactions. Yet, it is still unclear how the perception of threat by competitors is related to the specific content of the announcement. This study explores the actual content of NPAs observed in a particular market. This is done through a multi-year content analysis of new-product announcements in the DRAM memory chip industry. The study analyzes patterns in the occurrence of attributes and demonstrates how firm strategy affects NPA content. Findings from this study provide important insights for managers about the design of NPAs. It also triggers further research on the use of NPAs in competitive industrial markets.

Si–H Bond Breaking Induced Retention Degradation During Packaging Process of 256 Mbit DRAMs With Negative Wordline Bias

Data retention degradation of a 256-Mbit DRAM during the packaging process is investigated in this paper. Electrical measurement and device simulation show that a trap-assisted leakage degrades the retention time even in packaging process at about 250/spl deg/C. Retention time of the degraded chip is strongly dependent on the negative wordline voltage and operation temperature, but less sensitive to the substrate bias. Trap-assisted gate induced drain leakage is proposed as the mechanism of retention loss in the degraded chip. The degraded chips usually can be repaired by another thermal baking process. We propose Si-H bond breaking and the subsequent trap generation at the gate and drain overlap region as the root cause of retention degradation according to the fact that the Si-H bond density of backend passivation oxide and nitride layers correlate well with the retention performance of DRAM chips with negative wordline bias. Moreover, the packaged chip shows variable retention behavior during a thermal baking of 250/spl deg/C. Theoretical calculation indicates that the trap generation or movement to the high electrical field region beneath the gate can increase the trap-assisted gate induced drain leakage by about an order of magnitude.

Numerical analysis of deep-trap behaviors on retention time distribution of DRAMs with negative wordline bias

The data retention time characteristics of the DRAM cell with the negative wordline bias are investigated. With the unique characteristics shown in the gate-induced drain leakage current and the data retention time distribution of the 256-Mb DRAM chip, a model for the sensitivity of data retention time to gate bias is proposed. With the help of two-dimensional device simulation, we found that the relative trap energy (/spl Delta/E/sub t/) of the trap energy to intrinsic Fermi energy plays a key role to determine the retention time of a DRAM cell transistor for the weak cell as well as the normal cell. Also, it is shown the localized trap in the specific region having large electric field is responsible for abnormally large leakage current of the weak cell. An analytic formula for activation energy for the weak cell and the normal cell are also proposed to estimate trap energy level in real device.

An industrial evaluation of DRAM tests

DRAM production tests are currently necessary to reach a defect-per-million level that approaches the single-digit numbers. This implies that a single memory test is insufficient; rather, a set of tests is necessary. This application of 40 well-known memory tests to 1,896 1-Mbyte /spl times/ 4 DRAM chips, used up to 48 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests - those covering more different functional faults - also have higher fault coverage.

Environmental impacts of microchip manufacture

Environmental impacts associated with the manufacture of semiconductor devices are characterized from two perspectives: a qualitative survey of key issues and quantitative analysis of energy and entropy associated with the processes in the production chain. The main issues of environmental concern are emissions from fabs, health effects on line workers and high energy and material use. Results of analysis of material use in the production chain suggest that total weight of secondary fossil fuel and chemical inputs to produce and use a single 2-g 32MB DRAM chip are 1600 and 72 g, respectively. Secondary inputs of fossil fuels to manufacture a chip total 600 times its weight, high compared to a factor of 1–2 for an automobile or refrigerator. Due to its extremely low-entropy, organized structure, the materials intensity of a microchip is orders of magnitude higher than that of “traditional” goods.

A class of random multiple bits in a byte error correcting and single byte error detecting (S/sub t/bEC-S/sub b/ED) codes

Correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single chip output and simultaneously detecting errors caused by single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit byte Error Detecting (S/sub t/b/EC-S/sub b/ED) codes which have the capability of correcting random t-bit errors occurring within a single b-bit byte and simultaneously indicating single b-bit byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S/sub 3/8/EC-S/sub 8/ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S/sub 3/8/EC-S/sub 8/ED code is capable of correcting errors caused by single subarray data faults, i.e., single 4-bit byte errors, as well. This paper also shows that perfect S/sub (b-t)/b/EC-S/sub b/ED codes, i.e., perfect S/sub t/b/EC-S/sub b/ED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.

Correlation prefetching with a user-level memory thread

This paper proposes using a user-level memory thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: The correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide applicability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.

The 1.7 kilogram microchip: energy and material use in the production of semiconductor devices.

The scale of environmental impacts associated with the manufacture of microchips is characterized through analysis of material and energy inputs into processes in the production chain. The total weight of secondary fossil fuel and chemical inputs to produce and use a single 2-gram 32MB DRAM chip are estimated at 1600 g and 72 g, respectively. Use of water and elemental gases (mainly N2) in the fabrication stage are 32,000 and 700 g per chip, respectively. The production chain yielding silicon wafers from quartz uses 160 times the energy required for typical silicon, indicating that purification to semiconductor grade materials is energy intensive. Due to its extremely low-entropy, organized structure, the materials intensity of a microchip is orders of magnitude higher than that of "traditional" goods. Future analysis of semiconductor and other low entropy high-tech goods needs to include the use of secondary materials, especially for purification.