Drain Terminals Research Articles

A Synaptic Transistor Based on Monolayer Monocrystalline‐MoS2 for Neuromorphic Applications

Ultrathin 2D semiconductor materials have attracted tremendous attention due to their potential application in neuromorphic computing, especially for electronic devices with high stability and low energy consumption. Two‐terminal memristors cannot extend the range of functionalities for complex neuromorphic applications due to their inherent single presynaptic input; thus three‐terminal synaptic transistors based on monolayer monocrystalline‐MoS2 films grown by chemical vapor deposition (CVD) are fabricated in this work. Importantly, there are two modes including drain and gate dual tunability available in nonvolatile memory functions. Both drain terminal and gate terminal can be used as presynaptic inputs to successfully simulate excitatory/inhibitory postsynaptic current (EPSC/IPSC), spike‐amplitude‐dependent plasticity (SADP), spike‐timing‐dependent plasticity (STDP), and long‐term plasticity (LTP) of biological synapses, providing multiple degrees of freedom for synaptic weight modulation. The conductance modulation of drain and gate terminals can be attributed to the migration and charges trapping/detrapping process of sulfur vacancies. Using monocrystalline‐MoS2 films, the device not only attains a lower operation voltage and a higher endurance (5000 cycles), but exhibit low energy consumption during the LTP process (≈3.75 pJ) with the gate terminal, indicating more flexibility and great potential of complex neuromorphic application.

Development of compact inductive energy storage pulsed-power generator driven by 13 kV SiC-MOSFET.

A compact inductive energy storage (IES) pulsed-power generator that is driven by a novel 13 kV silicon carbide (SiC)-MOSFET is developed and molded into a compact modified TO-268. In this article, the switching characteristics required for IES pulsed-power generator development are evaluated. The maximum slew rates at MOSFET turn-on and turn-off are 157 and 129 kV/μs, respectively, at an input voltage of 10 kV. The maximum current flow from the drain to the source terminal is limited to 128A during short-circuit switching. The on-resistance between the drain and source terminals increases during the SiC-MOSFET's on state. It increases with the voltage and its minimum value is 1.07 Ω. These characteristics show that the device is suitable for use as an opening switch because of its low on-resistance and rapid large-current cutoff at high operating voltages. The characteristics of an IES pulsed-power generator composed of a SiC-MOSFET, a capacitor, and a pulsed transformer with a turn ratio of 5:15 are also evaluated. The output voltage peak and full width at half maximum reach 31.4 kV and 55ns, respectively, at a charging voltage of 1100V. The maximum energy transfer efficiency is 50.2% of the input energy with a load resistance of 2.5 kΩ. The results show that the MOSFET has excellent potential to support the development of a compact plasma generation system that offers better performance pulsed-power generators driven by semiconductor devices.

Is it Unjustified to Perform Segmentectomy in Surgical Treatment of Lung Adenocarcinoma?

The aim of our study differs from similar studies since we compared superiority and similarity of segmentectomy performed for early-stage lung cancer over lobectomy in terms of clinical and oncological results. The data from 294 patients who underwent anatomical resection due to primary lung cancer were retrospectively reviewed. Data from 99 patients who underwent lobectomy and segmentectomy due to early-stage lung adenocarcinoma were analyzed. Patients were divided into two groups: 84 patients undergoing lobectomy and 15 patients undergoing segmentectomy. Both groups were analyzed in terms of epidemiological, surgical and oncological results, by comparing several parameters. The most common postoperative complication was observed in the respiratory system. In total, 25 complication (29.8%) in the lobectomy group and 3 complications (20%) in the segmentectomy group were observed related to the postoperative respiratory system (P = 0.546). There was no statistically significant difference between the two groups in terms of recurrence-metastasis during follow-up, chemotherapy-radiotherapy condition and mortality. Main discharge time and thorax drain termination time were shorter in the segmentectomy group (P = 0.011 and P = 0.033, respectively). There was no statistically significant difference between the two groups in terms of postoperative survival or disease-free time (P = 0.361 and P = 0.461, respectively). If there is no contraindication, segmentectomy can be considered as the surgical treatment for lung adenocarcinomas with tumor size of 2 cm or less and a minimum 1 cm clean surgical margin.

5‐2: Enhanced Bending Endurance with Transverse Tensile Strain and 4‐Terminal Double Gate LTPS TFTs for flexible AMOLED

This letter investigates the degradation behavior of p‐channel LTPS TFTs on PI substrate under the static bending stress. During 1hr bend, the threshold voltage shifts positively and the subthreshold slope increases slightly. In transverse compressive strain, the field effect mobility increases abruptly with the decrease of the effective channel length and the off state leakage current. This is attributed to the generation of the strain‐induced GI defects near the source and drain terminals, resulting in the trapping of electrons and a shrinkage of the effective channel length and the H passivation of the strained Si bonds in the channel. By inserting the bottom metal layer to block the H diffusion from PI substrate, the controllable normal NBTI behavior is observed in a strained LTPS TFT on PI. These transverse tensile strained and 4‐termianl double gate LTPS TFTs on PI shows as a stable switching TFTs on PI for the flexible system‐on‐panel display.

Operational Transconductance Amplifier-Based Electronically Controllable Memcapacitor and Meminductor Emulators

In this paper, two simple circuits are presented to emulate both memcapacitor and meminductor circuit elements. The emulation of these components has crucial importance since obtaining these high-order elements from markets is difficult when compared to resistor, capacitor and inductor. For this reason, we proposed Multi-Output Operational Transconductance Amplifier (MO-OTA)-based electronically controllable memcapacitor and meminductor circuits. To operate the MOS transistor as a capacitor, drain and source terminals are connected to each other. The memcapacitor behavior is obtained by driving the connected terminals with suitable voltage values. Only a few active and grounded passive components which are found in markets easily are used to emulate meminductive behavior. Furthermore, all passive elements in the circuit are grounded. All simulation results for memcapacitor and meminductor emulators are obtained successfully when compared to previous studies. For all analyses, MO-OTA is laid using the Cadence Spectre Analog Environment with TSMC 0.18[Formula: see text][Formula: see text]m process parameters and occupied a layout area of only 86.21[Formula: see text][Formula: see text]m.

Design of an Extreme Low Cutoff Frequency Highpass Frontend for CMOS ISFET via Direct Tunneling Principle

In this work, ISFET frontends utilising the direct tunneling current to eliminate trapped charge are proposed. The principle has been investigated and verified via silicon-imitated ISFET first, where silicon capacitors are used to imitate the passivation ones. Because the dominant tunneling components depend on the potential difference between Gate and Drain terminals, a source-follower structure could itself perform a highpass filter with time constant at 10-100 seconds level. Additionally, a time-constant regulation mechanism is presented by feeding the output signal back to the drain terminal of ISFETs, achieving a regulation factor over 50, namely from 4.7 seconds to 243.4 seconds in our implementation. Afterwards in chemical test, proposed ISFETs have been verified in terms of unit passivation capacitance, linearity, noise and sensitivity for ISFETs with 3 different top metal areas. It is found that approximately 30 mV/pH sensitivity can be achieved, and for the first time we managed to derive the relation between chemical flicker noise and sensing metal area.

Intrinsic polarization coupling in 2D α‐In2Se3toward artificial synapse with multimode operations

AbstractEmulation of advanced synaptic functions of the human brain with electronic devices contributes an important step toward constructing high‐efficiency neuromorphic systems. Ferroelectric materials are promising candidates as synaptic weight elements in neural network hardware due to their controllable polarization states. However, the increased depolarization field at the nanoscale and the complex fabrication process of the traditional ferroelectric materials hamper the development of high‐density, low‐power, and highly sensitive synaptic devices. Here, we report the implementation of two‐dimensional (2D) ferroelectric α‐In2Se3as an active channel material to emulate typical synaptic functions. The α‐In2Se3‐based synaptic device features multimode operations, enabled by the coupled ferroelectric polarization under various voltage pulses applied at both drain and gate terminals. Moreover, the energy consumption can be reduced to ~ 1 pJ by using high‐κdielectric (Al2O3). The successful control of ferroelectric polarizations in α‐In2Se3and its application in artificial synapses are expected to inspire the implementation of 2D ferroelectric materials for future neuromorphic systems.

Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

Analysis of single electron transistor using switched capacitor filter

This paper deals with electrical characteristic of Single-Electron Transistor (SET). The Current- voltage (I-V) characteristic of the SET is predicted according to various capacitance parameters. The Process of simulation is based on analytical transistor model. The effect of tunnelling capacitance on the I-V characteristics of SET are systematically computed assuming source and drain are connected by quantum dot. The Steady state equation is solved by considering the tunnelling mechanism. We calculated free energy changes as a function of equivalent circuit parameters and background charge. Tunnelling probabilities on drain and source terminals are determined using Fermi’s Golden Rule. The SET is the simplest device wherein coulomb blockade effect can be observed.

DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package

This paper shows that an intermittent AC coupling defect occurring in a DDR4 data channel will cause more intermittent errors in DDR4, compared to such defect in DDR3. The intermittent AC coupling defect occurs due to intermittent fracture in DDR4 package solder ball. The defect causes DC offset in DDR4, which shifts the data signal or data eye and results in DDR4 data channel failure. The DC offset occurs due to the asymmetric nature of pseudo open drain termination scheme. DDR4 data channel response is compared with DDR3 channel. It is shown that pseudo random binary sequence (PRBS) pattern will always cause failure for DDR4, but PRBS will only cause failure in DDR3 if the sequence of consecutive 0’s or 1’s in PRBS pattern is long enough to cause threshold violation. As a result there will be more intermittent errors in DDR4 compared to DDR3. The defect due to fracture in solder ball is modelled by an AC coupling capacitor. A 1nF AC coupling capacitor corresponding to a solder ball fracture of height about 1nm is used to show the difference between DDR4 and DDR3 response.

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

In this report, we study nonlinear electrical behaviors found in vertical-architecture transistors based on wrap-around-gated gallium nitride (GaN) nanowires (NWs) by extending a one-dimensional case of the Landauer-Buttiker formula. Here, the GaN NWs are considered “almost” one-dimensional ideal wires connecting the drain and source terminals, with the gate terminal serving to control the flowing current. Unlike previous models, which require several parameters and complex calculations, our proposed model only needs three parameters and simple calculations to match the experimental data. With this model, we confirm that the maximum current before saturation is a consequence of quasi-ballistic drain current. Thus, electron mobility has no effect in this device. Using a simple formulation, we discuss gating hysteresis in the device that is mediated by the selected oxide layer interface. We show that the memory effect of the device is attributed to time-delay current. The shorter gate length increases the transmission coefficient. As a result, the model can be employed to predict the next-generation NW transistor performance.

STUDY ELECTROMAGNETIC WAVE INTERACTION OF ACTIVE-MATRIX THIN FILM TRANSISTORS

Active-matrix thin film transistors (TFTs) on glass substrates with a metal backplane, that are applied for flat panel displays, can be considered as a metamaterial absorber. In this study, TFT structures using doped silicon at source, drain, and channel terminals are investigated. These terminals are unchanged in size of 75 µm square and thickness of 5.3 µm. The electric conductivity is varied at the channel. The simulation results show that the structures with 500 S\m electric conductivity channels absorb incident electromagnetic waves with appropriately 100% at 758 GHz and a wide bandwidth of 20 GHz. As the electrical conductivity increases, the absorption and bandwidth are smaller at the main resonance peak. As the electrical conductivity decreases, the absorption falls at the resonance frequency, but the bandwidth is broadened. In addition, the electric field in the channel may influence the electron in the semiconductor and the electrical current between the source and drain terminals. By observing the electric field at the resonance frequency, we found that it is focused on the sides of channel terminals.

Study on Characteristics of Enhancement-Mode Gallium-Nitride High-Electron-Mobility Transistor for the Design of Gate Drivers

An enhancement-mode gallium-nitride high-electron-mobility transistor (E-mode GaN HEMT) operated at high frequency is highly prone to current spikes (di/dt) and voltage spikes (dv/dt) in the parasitic inductor of its circuit, resulting in damage to the power switch. To highlight the phenomena of di/dt and dv/dt, this study connected the drain, source, and gate terminals in series with inductors (LD, LS, and LG, respectively). The objective was to explore the effects of di/dt and dv/dt phenomena and operating frequency (fS) on drain-to-source voltage (Vds), drain-to-source current (Ids), and gate-to-source voltage (Vgs). The experimental method comprised two projects: (1) establishment of a measurement system to assess the change of electrical characteristics of the E-mode GaN HEMT and (2) change of the fS and the inductances (i.e., LD, LS, and LG) in the circuit to measure the changes in Vds, Ids, and Vgs, thus summarizing the experimental results. According to the experimental results on electrical characteristics, a gate driver circuit may be designed to drive and protect the E-mode GaN HEMT while being actually applied to a 120-W synchronous buck converter with an output voltage of 12 V and an output current of 10 A.

A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

High performance ammonia gas sensor based on GaN honeycomb nanonetwork

In this work, we have demonstrated a FET-like ammonia (NH3) gas sensor fabricated on a unique structure namely GaN honeycomb nanonetwork (GaN-HN) which is in-plane electrically conductive together with large surface-to-volume ratio. Utilizing ohmic contact Ti/Al/Ti/Au multilayers as the source and the drain terminals and Pt nanonetwork layer as the gate terminal, the FET-like NH3 gas sensors were fabricated by a two-mask photolithography process. The fabricated NH3 gas sensors have high selectivity, fast response/recovery, and a wide detection range up to 5000 ppm. The response and recovery time for 5 ppm NH3 gas are 23 s and 101 s at a moderate operating temperature of 120 °C. Interestingly, this sensor is capable to detect trace NH3 gas and the low limit of detection (LOD) is as small as 0.31 ppm. Its absorption activation energy Ea is also investigated by the transient-state study.

A theoretical modeling analysis for triboelectrification controlled light emitting diodes

Abstract In this paper, we demonstrate the use of triboelectric nanogenerator (TENG) as a mean of mechanical light triggering to control InGaN-based light-emitting diodes (LEDs). Light extraction from the LED is two successive steps process. First, the voltage produced by the TENG is used to control the gate-to-source current of a MOSFET transistor through adjusting the transistor channel width and length. The second step is forwarding the drain-source current resulting from MOSFET transistor to the LED as its injection current to induce spontaneous emission from the LED surface to the air. Three LED colors are considered: red, green and blue. Significant emitted power from these InGaN-based LEDs in the RGB wavelength band is observed for both P-MOSFET and N-MOSFET transistor configurations. The emitted optical spectrum is controlled by optimizing the combined TENG-MOSFET-RGB LED geometry; dimensions and the bias voltage between the drain and source terminals of the MOSFET transistor. With recent advances in TENGs as an energy harvesting technology, it is expected that this study offers an approach to enhance the light extraction of various LED devices. With the enhancements in the performance of optoelectronic devices, the field of tribo-phototronics has attracted more attention, and in this work, we introduce the first theoretical framework, to the best of our knowledge, based on finite element modeling. This study provides significant insights into the working principles of tribo-Phototronic devices as well as guidelines for future device design.

Ion Gel‐Gated Nonvolatile Formation of Lateral MoTe2 Diode for Self‐Powered Near‐Infrared Photodetection

Electrostatic gates by ion liquid (IL) or ion gel (IG) have allowed the exploration of intriguing material properties that are related to heavy charge doping in low‐dimensional materials. However, the obtained gate modulation is usually volatile at room temperature due to the recovery of ion position when removing the gate bias, which hinders their application in practical functional devices. Herein, the electrochemical IG gate is explored, and a nonvolatile modulation of the doping polarity of MoTe2 (from n to p and reversibly to n) by exploiting the electrochemical hydrolysis of residual water in IG and the subsequent chemical ion adsorption on MoTe2 is demonstrated. Further, based on the asymmetrically coupled gate bias to source and drain terminals, a lateral pn diode is prepared with long‐term stability >5 × 104 s and a self‐powered responsivity >85 mA W−1 at the near‐infrared wavelength of 1050 nm. The performance of diode is further optimized by applying a slight gate bias that tunes the width, position of space charge region in junction, and the overall charge collection efficiency. The nonvolatile electrochemical IG gate thus offers a viable pathway toward 2D low‐power photodetectors in the infrared spectra range.

Piezoelectric energy harvesting from DC-DC converters

Energy harvesting from piezoelectric is proved to be a viable technology to source low power electronic devices. In this paper, piezoelectric energy harvester is designed such that the energy is harvested by utilizing the switching of the MOSFET in DC-DC converter, which becomes an integral part of modern industrial equipment. Energy harvesting is realized by piezoelectric and converse effect of piezoelectric material. The harvester is designed to have transmitter and receiver piezoelectric separated by metal plate, connected across the drain and source terminals of the MOSFET. The performance of the harvester is experimentally evaluated with boost converter for supercapacitor storage.

Analysis of Nonlinear Power Distribution Network and Estimation of Jitter Transfer Functions Based on Output Buffer Pseudo Open Drain Termination

With increasing data rates of links, jitter budget allowable for the channel keeps decreasing, and precisely estimating jitter becomes very important to have confidence in designing a robust communication system. Current analysis of jitter transfer function assumes a linear or approximately linear power distribution network, but the linearity of power distribution network can be distorted by driver states or load conditions at the end of signal channel. In order to estimate power supply induced jitter accurately, both the receiver termination mode and the interconnection parameters of channel should be considered. In this paper, the nonlinearity of power distribution network caused by termination mode and its effect on jitter are discussed. The emphasis is given to the pseudo open drain termination, which is the popular scheme used in DDR4. Then, an analytical calculation method of transfer functions relating power supply noise to jitter is proposed, in which the nonlinear power distribution network model including the output buffers, signal channels, and pseudo open drain terminations is used to derive the analytical expressions. Simulation results demonstrate that the proposed analytical estimation method achieves good agreement with ADS simulated results under a real case power distribution network.

Analytical determination of atypical quantized resistances in graphene p-n junctions

A mathematical approach is introduced for predicting quantized resistances in graphene p-n junction devices that utilize more than a single entry and exit point for electron flow. Depending on the configuration of an arbitrary number of terminals, electrical measurements yield nonconventional, fractional multiples of the typical quantized Hall resistance at the ν=2 plateau (RH≈ 12906 Ω) and take the form: abRH. This theoretical formulation is independent of material, and applications to other material systems that exhibit quantum Hall behaviors are to be expected. Furthermore, this formulation is supported with experimental data from graphene devices with multiple source and drain terminals.