Drain Resistance Research Articles

Effect of oxide traps on channel transport characteristics in graphene field effect transistors

A semiempirical model describing the influence of interface states on characteristics of gate capacitance and drain resistance versus gate voltage of top gated graphene field effect transistors is presented. By fitting our model to measurements of capacitance–voltage characteristics and relating the applied gate voltage to the Fermi level position, the interface state density is found. Knowing the interface state density allows us to fit our model to measured drain resistance–gate voltage characteristics. The extracted values of mobility and residual charge carrier concentration are compared with corresponding results from a commonly accepted model which neglects the effect of interface states. The authors show that mobility and residual charge carrier concentration differ significantly, if interface states are neglected. Furthermore, our approach allows us to investigate in detail how uncertainties in material parameters like the Fermi velocity and contact resistance influence the extracted values of interface state density, mobility, and residual charge carrier concentration.

Bottom-gate poly-Si thin-film transistors by nickel silicide seed-induced lateral crystallization with self-aligned lightly doped layer

We report a novel method to reduce source and drain (S/D) resistances, and to form a lightly doped layer (LDL) of bottom-gate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). For application in driving TFTs, which operate under high drain voltage condition, poly-Si TFTs are needed in order to attain reliability against hot-carriers as well as high field-effect mobility (μFE). With an additional doping on the p+ Si layer, sheet resistance on S/D was reduced by 37.5% and an LDL was introduced between the channel and drain. These results contributed to not only a lower leakage current and gate-induced drain leakage, but also high immunity of kink-effect and hot-carrier stress. Furthermore, the measured electrical characteristics exhibited a steep subthreshold slope of 190mV/dec and high μFE of 263cm2/Vs.

Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET

Separate extraction of source ( $R_{\mathrm{ S}})$ from drain resistance ( $R_{\mathrm{ D}})$ is important in the systematic modeling of electrical characteristics and investigation of physical mechanism related to the performance and reliability in MOSFETs and their integrated circuits. We report a hybrid open drain method (ODM), as a fully current-based characterization technique, for a comprehensive separation of asymmetric source and drain resistance components in a single MOSFET. In the hybrid ODM, the ODM through the parasitic bipolar transistor is combined with the dual-sweep combinational transconductance technique, the channel resistance method, and the parasitic junction current method. We fully considered the asymmetry in the source and the drain possibly caused by the layout, process, and degradation under bias. We successfully extracted the resistance components with $R_{\mathrm {{Se}}} = 6.66{{-}}7.35~\Omega $ , $R_{\mathrm {{De}}} = 7.64{{-}}8.34~\Omega $ , $R_{\mathrm {{So}}} = 0.78{{-}}8.07~\Omega $ , $R_{\mathrm {{Do}}} = 1.11{{-}}10.08~\Omega $ , and $R_{\mathrm {{SUB}}} = 6.29{{-}}9.17~\Omega $ in the n-channel MOSFETs. $R_{\mathrm {{Se}}}~(R_{\mathrm {{De}}})$ is the $V_{\mathrm {{GS}}}$ -independent external source (drain) resistance. $R_{\mathrm {{So}}}~(R_{\mathrm {{Do}}})$ is the $V_{\mathrm {{GS}}}$ -independent external spreading source (drain) resistance and $R_{\mathrm {{Si}}}~(R_{\mathrm {{Di}}})$ is the $V_{\mathrm {{GS}}}$ -dependent intrinsic source (drain) resistance, respectively. $R_{\mathrm {{SUB}}}$ is the substrate resistance. The hybrid ODM is expected to be useful in the characterization of parasitic resistances in each MOSFET with asymmetry caused by the layout, process, and degradation without using multiple devices with different channel length ( $L$ ) and width ( $W$ ) for measurement.

Reduced parasitic contact resistance and highly stable operation in a-In-Ga-Zn-O thin-film transistors with microwave treatment

In this work, we studied the effects of microwave annealing process on amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and demonstrated a high performance and reliable device characteristics. The characteristic trapping time (τ) derived from stretched-exponential model was extracted to exhibit the quality improvement of a-IGZO thin film. The microwave annealing features a selective heating and potentially avoids the damage to materials neighboring the a-IGZO channel layer in TFT device structure during thermal processes, resulting in lower parasitic source to drain resistance.

The causes of GaN HEMT bell-shaped transconductance degradation

Modern communication systems require high linearity, usually in addition to high output power. High linearity requires a flat device transconductance (gm) vs. gate-source voltage (Vgs), while at the same time, transconductance must be high for high gain. In spite of much research to investigate device/system linearity, GaN high electron mobility transistor (HEMT) devices generally show a bell-shaped gm curve characteristic much like other FET devices. In this study, we examine gm behavior and conclude that the bell-shaped gm is caused by: (1) devices operating in the linear region, generally under low to moderate Vds bias, (2) nonlinear source and drain resistances, and (3) self-heating thermal effects. When Ids no longer follows a linear increase with Vgs due to these three causes, gm decreases and forms a bell shape. The key to maintain the gm flatness is to reduce both parasitic electrical and thermal resistances.

High-Performance Asymmetric Underlap Ge-pTFET With Pocket Implantation

This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current ( $I_{\mathrm{\scriptscriptstyle OFF}})$ of 50-nm Ge-pTFETs to about 3.27 pA/ $\mu \text{m}$ without degrading the ON-current ( $I_{\mathrm{\scriptscriptstyle ON}})$ , and a p+ pocket doping improves the ion of these devices to about 0.295 mA/ $\mu \text{m}$ without compromising $I_{\mathrm{\scriptscriptstyle OFF}}$ . The analog and RF performances of the drain-underlapped Ge-pTFETs are investigated in terms of the drain current, transconductance, output resistance, intrinsic gain, cutoff frequency, and maximum frequency of oscillation for pocket-doping length varying from 0 to 6 nm. In addition, the influence of the pocket doping on the nonquasi-static performance is analyzed in terms of the gate–source and gate–drain capacitances, gate–drain resistance, and intrinsic delay time. Finally, the performance of the source-pocket drain-underlapped Ge-pTFETs in ICs is studied using a common source amplifier.

Comparisons between Dual and Tri Material Gate on a 32 nm Double Gate MOSFET

The paper reports a comparative analysis between the dual material gate double gate (DMG-DG) nMOSFET and the tri material gate double gate (TMG-DG) nMOSFET in terms of their analog and RF performance. Three different devices having the DMG-DG structure have been considered. Each of the devices have different higher workfunction material gate length (L1) to lower workfunction material gate length (L2) ratio (L1:L2). Along with the three devices, the performance of the TMG-DG nMOSFET is compared. The analog parameters considered for the comparison are the drain current ([Formula: see text]), the transconductance ([Formula: see text]), the transconductance generation factor ([Formula: see text]/[Formula: see text]) and the intrinsic gain ([Formula: see text]Ro). The drain induced barrier lowering (DIBL) of the devices is compared. The RF analysis is performed using the non quasi static (NQS) approach. We consider the intrinsic gate to source capacitances ([Formula: see text]), the intrinsic gate to drain capacitance ([Formula: see text]), the intrinsic gate to source resistances ([Formula: see text]), the intrinsic gate to drain resistance ([Formula: see text]), the transport delay ([Formula: see text]), the unity current gain cut-off frequency ([Formula: see text]) and the max frequency of oscillation ([Formula: see text]) for the RF comparisons. A single stage amplifier is also implemented using the devices for a circuit comparison.

Voltage Amplifier Based on Organic Electrochemical Transistor

Organic electrochemical transistors (OECTs) are receiving a great deal of attention as amplifying transducers for electrophysiology. A key limitation of this type of transistors, however, lies in the fact that their output is a current, while most electrophysiology equipment requires a voltage input. A simple circuit is built and modeled that uses a drain resistor to produce a voltage output. It is shown that operating the OECT in the saturation regime provides increased sensitivity while maintaining a linear signal transduction. It is demonstrated that this circuit provides high quality recordings of the human heart using readily available electrophysiology equipment, paving the way for the use of OECTs in the clinic.

Electrical Degradation of InAlN/GaN HEMTs Operating Under ON Conditions

The degradation of InAlN/GaN high-electron-mobility transistors (HEMTs) for millimeter-wave applications has been examined under on conditions. Two dominant permanent degradation mechanisms have been identified as well as two trapping mechanisms which affect the device characteristics in different ways. Under high-voltage, low-current stress conditions, we have observed permanent enhancement in the maximum drain current $I_{D\mathrm {{max}}}$ that arises from a negative shift in threshold voltage $V_{T}$ . We attribute this mechanism to depassivation of hydrogenated defects. Under the same stress conditions, there is prominent and reversible hot-electron trapping on the drain side of the device that brings $I_{D\mathrm {{max}}}$ down and increases the drain resistance. Under low-voltage high-current stress conditions, there is a visible permanent reduction in $I_{D\mathrm {{max}}}$ and a positive shift in $V_{T}$ . This is also the signature of-high temperature stress under unbiased conditions and is attributed to gate sinking.

A transformed analytical model for thermal noise of FinFET based on fringing field approximation**Project supported in part by the All India Council for Technical Education (AICTE).

This paper delineates the effect of nonplanar structure of FinFETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended (underlap) S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional (3-D) structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 dB and 100 Ω respectively and optimum admittance increases to 5.45 mƱ at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.

A Physics-Based Compact Model of SiC Power MOSFETs

The presented compact model of SiC power MOSFETs is based on a thorough consideration of the physical phenomena which are important for the device characteristics and its electrothermal behavior. The model includes descriptions of the dependence of channel charge and electron mobility on the charge of interface traps and a simple but effective calculation of the voltage-dependent drain resistance. Comparisons with both physical 2-D device simulations and experiments validate the correctness of the modeling approach and the accuracy of the results.

Modeling and simulation of single electron transistor with master equation approach

In this paper, we discuss modeling and simulation of single dot Single Electron Transistor (SET) using master equation approximation. For SET modeling and simulation, master equation method treats the electron tunneling and its transition probabilistically. The probability of electron tunneling is used to determine the current density in accordance with selected input parameters. The calculation results show fairly accurate electrical characteristics of SET as compared with experimental data. Staircase pattern from I-V are clearly obtained as the main role of coulomb blockade effect in SET system. We also extend our calculation by introduce some additional parameters such as; the effect of working temperature, gate voltage dependent, and the influence of resistance to the device characteristic. We found that increasing operational temperature will promote higher current density, both in forward and reverse bias region. In the case of using single dot with 30 nm × 80 nm × 125 nm dimension, coulomb blockade effect could be reduced by applying gate voltage higher than 3V and setting drain resistance higher than source's. Our studies show an alternative approach in modeling and simulation of electronic devices and could be potential for development of novel nanoelectronic devices.

A general solution for vertical-drain consolidation with impeded drainage boundaries

An analytical solution is derived from the generalized governing equations of equal-strain consolidation with vertical drains under multi-ramp surcharge preloading. The hydraulic boundary conditions at both top and bottom of the consolidating soil are modelled as impeded drainage. The impeded drainage is described by using the third type boundary condition with a characteristic factor of drainage efficiency. Fully drained and undrained boundary conditions can also be modelled by applying an infinite and a zero characteristic factor, respectively. Simultaneous radial and vertical flow conditions are considered, together with the effects of drain resistance and smear. An increase in total stress due to multi-ramp loading is reasonably modelled as a function of both time and depth. A solution to calculate excess pore-water pressure at any arbitrary point in soil is derived, and the overall average degree of consolidation is obtained. It shows that the proposed solution can be used to analyze not only vertical-drain consolidation but also one-dimensional consolidation under either one-way or two-way vertical drainage conditions. The characteristic factors of drainage efficiency of top and bottom boundaries have a potentially important influence on consolidation. The boundary may be considered fully drained when the characteristic factor is greater than 100 and fully undrained when the characteristic factor is less than 0.1. The stress distribution along depth induced by the surcharge loading has a limited effect on the overall average degree of consolidation. However, it has a significant effect on the dissipation of excess pore-water pressure.

High-frequency performances of superjunction laterally diffused metal–oxide–semiconductor transistors for RF power applications

This paper presents the dc and high-frequency performances of laterally diffused metal–oxide–semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-µm CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers.

A Separate Extraction Method for Asymmetric Source and Drain Resistances Using Frequency-Dispersive C-V Characteristics in Exfoliated MoS2FET

Asymmetric source and drain (S/D) series resistances ( $R_{S}$ and $R_{D}$ ) are unavoidable in exfoliated MoS2 field-effect transistors (EM-FETs). Through combining the capacitance–voltage ( $C$ – $V$ ) and current–voltage characteristics, the asymmetric $R_{S}$ and $R_{D}$ values are extracted separately. First, the frequency-dispersive $C$ – $V$ characteristics are analyzed in a frequency range of 0.3–10 kHz. Second, the intrinsic $R_{S}$ and $R_{D}$ values ( $R_{S,int}$ and $R_{D,int})$ are characterized through deembedding the parasitic pad capacitances ( $C_{Pad} = C_{S,Pad}+C_{D,Pad})$ between the S/D metal and the bottom gate (G) in an overlapped region with the consideration of the structure-dependent parameters in the EM-FET. The proposed methodology is verified through comparison with the well-known channel resistance method, which is based on only the $I_{D}$ – $V_{D}$ characteristics in the linear region. Finally, $R_{S,int}$ and $R_{D,int}$ at various parasitic overlap areas are extracted separately with improved accuracy.

Numerical Simulation of Plasma Oscillation in 2-D Electron Gas Using a Periodic Steady-State Solver

The terahertz oscillation due to the plasma instability in the 2-D electron gas is numerically investigated using an in-house developed device simulator, G-Device. In order to overcome practical difficulties in the conventional transient simulation, a periodic steady-state (PSS) solver is implemented. The full Newton–Raphson scheme is applied to a set of discretized equations sampled at various time points during an oscillation period. Numerical results show that there is a threshold value of the injection velocity that allows the PSS oscillation. Moreover, the impact of the drain load resistance on the oscillation amplitude is estimated. It is found that considerable amplitude of the voltage oscillation can be achieved even with finite drain resistances. Although the growth rate of the voltage oscillation exhibits its maximum value with the infinite drain resistance, the maximum output power is obtained at a finite drain resistance.

A new analytical technique for extraction of bias‐dependent drain resistance in GaAs and GaN HEMTs

ABSTRACTTo improve the quality of transistor modeling, the nonlinear behavior of each element of the equivalent circuit must be known. There are few works devoted to the extraction of bias‐dependent drain resistance Rd, which strongly affects the transistor modeling. In this work, a new analytical technique for the extraction of bias‐dependent drain resistance in HEMT small signal model (SSM) is proposed. The efficiency of the new technique is demonstrated for GaN and GaAs HEMTs. It is shown that the new approach leads to the better SSM accuracy in the range of DC biases as compared to the widespread extraction methods. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2536–2539, 2015

Vertical-drain consolidation using stone columns: An analytical solution with an impeded drainage boundary under multi-ramp loading

An analytical solution is derived to predict consolidation with vertical drains under impeded drainage boundary conditions and multi-ramp surcharge loading. The impeded drainage is modelled by adopting the third type boundary condition with a dimensionless characteristic factor of drainage efficiency developed by Gray (1945) for one-dimensional consolidation. Fully drained and undrained boundary conditions can also be modelled by applying an infinite and a zero characteristic factor, respectively. The combined effects of drain resistance and smear are taken into account fully. An explicit, rigorous analytical solution is derived using the method of separation of variables to calculate excess pore-water pressure at any arbitrary point in soil and to derive the overall average degree of consolidation. The proposed solution can also be used to analyse one-dimensional consolidation without vertical drains but with an impeded drainage boundary. Its validity and accuracy are verified by comparing the proposed solution with the solutions developed by Gray (1945) and Terzaghi (1943). Its practical applicability is also evaluated by analysing a case history involving a fill embankment, which was constructed over a crust layer of hard soil overlying soft clay improved with stone columns. The crust layer is modelled as an impeded drainage. Reasonably good agreement is obtained between the consolidation results obtained from the proposed analytical solution and available three-dimensional finite-element predictions. With the further consideration of smear effects, good agreement is achieved between the consolidation results obtained from the proposed analytical solution and field measurements.

Mechanism of the self-changing parameters and characteristics in AlGaN/GaN high-electron mobility transistors after a step voltage stress**Project supported by the National Natural Science Foundation of China (Nos. 61376077, 61201046, 61204081), and the Beijing Natural Science Foundation (Nos. 4132022, 4122005).

The phenomenon of self-changing on the device parameters and characteristics after a step voltage stress was applied to the gate is studied in AlGaN/GaN high electron mobility transistors. The device was measured every 5 min after the stress was removed. The large-signal parasitic source (drain) resistance, transfer characteristics, threshold voltage, drain–source current, gate–source (drain) reverse current–voltage characteristics changed spontaneously after the removal of the stress. The time constant of the self-changing was about 25–27 min. The gate–source (drain) capacitance–voltage characteristics were constant during this process. Electrons were trapped by the surface states and traps in the AlGaN barrier layer when the device was under stress. The traps in the AlGaN barrier layer then released electrons in less than 10 s. The surface states released electrons continuously during the entire measurement stage, leading to the self-changing of mearsurement result.

An analytical solution for consolidation with vertical drains under multi-ramp loading

Various analytical solutions have been proposed for a unit-cell consolidation with a vertical drain under surcharge loading. These solutions involve different assumptions to address various aspects of consolidation. There is a lack of generalised solution for analysing consolidation of soil assisted by a vertical drain under various loading conditions. This paper presents a simplified solution for consolidation under multi-ramp loading. Generalised governing equations of equal-strain consolidation are solved. Simultaneous radial and vertical flow conditions, as well as the combined effects of drain resistance and smear, are taken into account fully. An increase in total stress due to multi-ramp loading is reasonably modelled as a function of both time and depth. An analytical solution to calculate excess pore-water pressure at any arbitrary point in soil is derived by using the method of separation of variables. The conventional definition of the degree of consolidation is given in terms of the dissipation of excess pore-water pressure as a result of the maximum increase in total stress in soil. This definition is interpreted in relation to the ultimate ground surface settlement due to surcharge preloading. Its validity and accuracy are verified by comparing the special cases of the proposed solution with two available analytical solutions. The proposed solution is also validated by a well-documented case history with settlement and pore-water pressure measurements. Reasonably good agreement is obtained. A new degree of dissipation is defined in terms of the dissipation of excess pore-water pressure as a result of currently induced increase in total stress in soil. By using this definition, an equation is proposed to estimate the gain in undrained strength of soil due to consolidation for assessing the stability of surcharge fills more effectively and correctly. The loading path over time and the compressibility of smeared soil are shown to have a potentially important influence on the degree of consolidation and the degree of dissipation.