Drain Resistance Research Articles

Performance Analysis of InP based Composite Channel e-mode HEMT Device for High Frequency Applications

High Electron Mobility Transistor (HEMT) is presently a very important part in the electronics industries for high frequency applications and for low power applications. In this approach, single gate enhancement mode composite channels of In0.7Ga0.3As/InAs/In0.7Ga0.3As HEMT devices are simulated and analyzed for low power operations which leads to strong DC and RF performance. This can be achieved by working on the composite channel which was lattice matched, gate which was recessed and length of the gate which was optimized. In this paper, for various lengths of the gate with constant barrier thickness, the performance of the device is analyzed symmetrically with the specialized device dimensions with thickness of the barrier (TB) = 2nm, thickness of the channel (TCH) = 15nm. The length of the gate can be reduced which supports in decreasing the drain resistance, effects of capacitance and improved average electron velocity in the gate. And this in turn results in the best performance of the device metrics with the values, trans-conductance (gm) as 1741 μS/μm, drain current (Id) as 0.553574 mA/μm, cut-off frequency (fT) as 431 GHz, maximum frequency of oscillations (fmax) as 557 GHz.

Study of Effective Graded Oxide Capacitance and Length Variation on Analog, RF and Power Performances of Dual Gate Underlap MOS-HEMT

Comparative analysis of a Symmetric Heterojunction Underlap Double Gate (U-DG) GaN/AlGaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) on varying the effective capacitance by using different oxide materials on source and drain sides, and determination of optimum length of oxides for the superior device performance has been presented in this work. This paper shows a detailed performance analysis of the Analog Figure of Merits (FoMs) like variation of Drain Current (IDS), Transconductance (gm), Output Resistance (R0), Intrinsic Gain (gmR0), RF FoMs like cut-off frequency (fT), maximum frequency of oscillation (fMAX), gate to source resistance (RGS), gate to drain resistance (RGD), gate to drain capacitance(CGD), gate to source capacitance (CGS) and total gate capacitance (CGG) using Non-Quasi-Static (NQS) approach. Power analysis includes Output power (Pout), Gain in dBm and power output efficiency (POE) have been studied. Studies reveal that the device with higher dielectric material towards source side shows superior performance. On subsequently changing the proportion of two oxides in a layer by varying length, it is observed that as the proportion of oxide increases the device demonstrates more desirable Analog and RF characteristics while best power performance is obtained from device with equal lengths of HfO2 and SiO2.

Finite Element Analysis of Equivalent Diameter of Prefabricated Vertical Drains

To clarify some of the inconsistencies in the research of equivalent diameter of PVDs, we constructed 3-D consolidation models of PVDs and sand drains using ABAQUS and compared models with and without sand drain resistance. When the sand drain resistance was included in the model, the equivalent diameters of the sand drains were 30, 65, 78, and 100 mm (for a 100-mm-wide, 4-mm-thick PVD) corresponding to PVD drainage depths (or soft soil layer thickness) of 2, 5, 8, and 10 m. Except for the depth of 2 m, the other results were higher than the values found in previous studies. The equivalent diameters increased with increasing consolidation depths. When the well resistance was ignored, the equivalent diameters were 20 mm for all the ground consolidation depths, which was less than the value in most previous research findings.

A Predistortion-Less Digital Transmitter With −50-dB ACLR Exploiting Output Conductance Linearization

Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Their linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and nonswitching driver cells. Often, digital predistortion (DPD) is required to transmit higher-order modulation schemes. In this letter, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. An SCPA with these driver cells is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process which demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of −50 dB and an error vector magnitude (EVM) of −45.5 dB for 5-MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.

Contact Resistance Induced Variability in Graphene Field Effect Transistors

The success of the graphene field-effect transistor (GFET) is primarily based on solving the problems associated with the growth and transfer of high-quality graphene, the deposition of dielectrics and contact resistance. The contact resistance between graphene and metal electrodes is crucial for the achievement of high-performance graphene devices. This is because process variability is inherent in semiconductor device manufacturing. Two units, even manufactured in the same batch, never show identical characteristics. Therefore, it is imperative that the effect of variability be studied with a view to obtain equivalent performance from similar devices. In this study, we undertake the variability of source and drain contact resistances and their effects on the performance of GFET. For this we have used a simulation method developed by us. The results show that the DC characteristics of GFET are highly dependent on the channel resistance. Also the ambipolar characteristics are strongly affected by the variation of source and drain resistances. We have captured their impact on the output as well as transfer characteristics of a dual gate GFET.

Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications.

In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

Alternating Current-Based Technique for Separate Extraction of Parasitic Resistances in MISFETs With or Without the Body Contact

We report a novel technique for separating the parasitic source (RS) and drain (RD) resistances in MISFETs using the open drain and the open source configurations based on an alternating-current(AC) signal. We conducted impedance analysis for the AC signal in the open drain for RS and the open source configuration for RD. The proposed technique is independent of the I-V equation of MISFETs with various influencing parameters for separate extraction of RS and RD through the physics-based equivalent circuit of MISFETs. So the proposed technique is applicable to every single device as long as the device is an insulated gate MISFET structure, regardless of the presence or absence of the body terminal. This technique is applied to amorphous oxide semiconductor thin-film transistors with the gate length =10μm without the body contact. As a result, parasitic resistances were separately extracted to be R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> = 2.1 kΩ, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 1.7 kΩ for W = 600μm, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> = R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> =1.1 kΩ for W = 1000μm, and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> = R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 0.6 kΩ for W = 2000μm independent of gate bias.

Simultaneously Defined Semiconducting Channel Layer Using Electrohydrodynamic Jet Printing of a Passivation Layer for Oxide Thin-Film Transistors.

A simple fabrication method for homojunction-structured Al-doped indium-tin oxide (ITO) thin-film transistors (TFTs) using an electrohydrodynamic (EHD) jet-printed Al2O3 passivation layer with specific line (WAl2O3) is proposed. After EHD jet printing, the specific region of the ITO film below the Al2O3 passivation layer changes from a conducting electrode to a semiconducting channel layer simultaneously upon the formation of the passivation layer during thermal annealing. The channel length of the fabricated TFTs is defined by WAl2O3, which can be easily changed with varying EHD jet printing conditions, i.e., no need of replacing the mask for varying patterns. Accordingly, the drain current and resistance of the fabricated TFTs can be modified by varying the WAl2O3. Using the proposed method, a transparent n-type metal-oxide-semiconductor (NMOS) inverter with an enhancement load can be fabricated; the effective resistance of load and drive TFTs is easily tuned by varying the processing conditions using this simple method. The fabricated NMOS inverter exhibits an output voltage gain of 7.13 with a supply voltage of 10 V. Thus, the proposed approach is promising as a low-cost and flexible manufacturing system for multi-item small-lot-sized production of Internet of Things devices.

Analytical solutions for the consolidation of unsaturated foundation with prefabricated vertical drain

SummaryBased on the consolidation theory raised by Fredlund, the solutions for the equal‐strain consolidation of unsaturated foundation with the prefabricated vertical drain considering smear effect and drain resistance are analytically formulated in this paper. Firstly, governing equations for excess pore pressures (i.e., excess pore‐air and pore‐water pressures) under the equal‐strain hypothesis are derived with the introduction of radial boundary conditions. Afterwards, the obtained coupled equations are solved by applying general integration, decoupling process, and Fourier sine series expansion. The smear coefficients and factors of drain resistance corresponding to air and water phases are both captured explicitly in the final solutions. Furthermore, the degenerated solutions are employed to verify the reliability of the current solutions. Finally, a parametric study is conducted to study the consolidation characteristics of the proposed foundation model against modeling sizes (S and N), smear coefficients (αa and αw), and drain resistance factors (Ga and Gw).

Temperature Effect On Behaviour of Photo Catalytic Sensor (PCS) Used For Water Quality Monitoring

The macro model for Photo Catalytic Sensor (PCS) proposed by Whig et al. (2014) has excellent improvement as it overcomes several problems like sophisticated designing, non-linearity, and long computation time found in the flow injection analysis (FIA). In this paper, the impact of variation in temperature on the behavior of novel PCS is presented. The paper proposes an approach for easy and fast operation optimization of the power of electronic devices using the Simulation Program with Integrated Circuit Emphasis (SPICE) model. The research studies include the effect of temperature on the threshold voltage, body leakage current, and the drain and source contact resistance. It mainly focuses on a more general user-friendly quick response time approach. Some exciting results, including the effect of change in the sensor output signal's strength with second-order parameters discussed above, are helpful during the fabrication of the device. The Simulation of PCS has been carried out in VLSI Lab, and experimental results are included to validate the findings. The results of the simulation were found to be somewhat in agreement with the theoretical predictions.

General Analytical Solution to Consolidation of Unsaturated Soil with Vertical Drain considering Drain Resistance

This paper presented a general analytical solution to consolidation of unsaturated soil with vertical drain considering drain resistance. Based on Fredlund’s one-dimensional consolidation theory and the equal-strain assumption, the coupled governing equations of excess pore-water and pore-air pressures are first decoupled by introducing two new variables. the method of eigenfunction and undetermined coefficients are then used to obtain the general solution under the drain resistance condition. Moreover, the good agreement between the equal-strain results and the typical free-strain results confirms the validity of the proposed solution. The consolidation behaviours, concluding average excess pore-air and pore-water pressures, are investigated against the drain resistance and the ratio of influence radius to vertical drain radius.

Gallium Nitride (GaN) High-Electron-Mobility Transistors with Thick Copper Metallization Featuring a Power Density of 8.2 W/mm for Ka-Band Applications.

Copper-metallized gallium nitride (GaN) high-electron-mobility transistors (HEMTs) using a Ti/Pt/Ti diffusion barrier layer are fabricated and characterized for Ka-band applications. With a thick copper metallization layer of 6.8 μm adopted, the device exhibited a high output power density of 8.2 W/mm and a power-added efficiency (PAE) of 26% at 38 GHz. Such superior performance is mainly attributed to the substantial reduction of the source and drain resistance of the device. In addition to improvement in the Radio Frequency (RF) performance, the successful integration of the thick copper metallization in the device technology further reduces the manufacturing cost, making it extremely promising for future fifth-generation mobile communication system applications at millimeter-wave frequencies.

The Dependence of the High-Frequency Performance of Graphene Field-Effect Transistors on Channel Transport Properties

This paper addresses the high-frequency performance limitations of graphene field-effect transistors (GFETs) caused by material imperfections. To understand these limitations, we performed a comprehensive study of the relationship between the quality of graphene and surrounding materials and the high-frequency performance of GFETs fabricated on a silicon chip. We measured the transit frequency (fT) and the maximum frequency of oscillation (fmax) for a set of GFETs across the chip, and as a measure of the material quality, we chose low-field carrier mobility. The low-field mobility varied across the chip from 600 cm2/Vs to 2000 cm2/Vs, while the fT and fmax frequencies varied from 20 GHz to 37 GHz. The relationship between these frequencies and the low-field mobility was observed experimentally and explained using a methodology based on a small-signal equivalent circuit model with parameters extracted from the drain resistance model and the charge-carrier velocity saturation model. Sensitivity analysis clarified the effects of equivalent-circuit parameters on the fT and fmax frequencies. To improve the GFET high-frequency performance, the transconductance was the most critical parameter, which could be improved by increasing the charge-carrier saturation velocity by selecting adjacent dielectric materials with optical phonon energies higher than that of SiO2.

On the DC extraction of the asymmetric parasitic source and drain resistances for MOSFETs

Two different parameter extraction methods are proposed in this article. First, a simple DC method is presented to extract the difference between the drain and source series resistance of MOSFETs. This method is valid for any three- or four-terminal MOSFET and it can be used in linear, triode or saturation region. Second, an integration-based method is proposed to extract the drain resistance and the source resistance of thin-film MOSFETs. Both methods were tested using simulated and measured data of two different devices: zinc oxide (ZnO) and polysilicon TFTs.

Analytical solution for free strain consolidation of stone column-reinforced soft ground considering spatial variation of total stress and drain resistance

This paper provides an analytical solution for consolidation problem of a stone column-improved soft soil layer subjected to an instantly applied loading under free strain condition. The radial and vertical consolidation equations are solved in a coupled fashion for both the stone column and its surrounding soil. A general solution of excess pore water pressure at any point of a unit cell model in terms of a Fourier-Bessel series was achieved using the combination of separation of variables method and orthogonal expansion technique. The obtained solution can capture the drain (well) resistance effect and the space-dependent distribution of total vertical stress induced by the external loading. Indeed, since the permeability and size of the stone column are directly utilised in the governing equations and the analytical solution, the drain resistance is directly captured. The capabilities of the proposed solution are exhibited through a comprehensive worked example, while the accuracy of the solution is verified against a finite element simulation and field measurements of a case history with good agreements. To examine the effect of various factors on consolidation behaviour of the composite ground, a parametric study involving column spacing, modulus and permeability of soft soil along with distribution pattern of total stress and thickness of soil layer is also conducted. A decrease in the column spacing or an increase in the modulus or permeability of soft soil led to the acceleration of the consolidation process of the soil region, while the variation of the total stress with depth and the thickness of soil deposit primarily affected the consolidation rate of stone column. Under the free strain condition, the average differential settlement between the stone column and encircling soil was indeed considerable during the consolidation process.

Investigation on Ambipolar Current Suppression Using a Stacked Gate in an L-shaped Tunnel Field-Effect Transistor.

L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because of increased off-current due to the large ambipolar current. In this paper, a stacked gate L-shaped TFET is proposed for suppression of ambipolar current. Stacked gates can be easily implemented using the structural features of L-shaped TFET, and on- and off-current can be controlled separately by using different gates located near the source and the drain, respectively. As a result, the suppression of ambipolarity is observed with respect to work function difference between two gates by simulation of the band-to-band tunneling generation. Furthermore, the proposed device suppresses ambipolar current better than existing ambipolar current suppression methods. In particular, low drain resistance is achieved as there is no need to reduce drain doping, which leads to a 7% enhanced on-current. Finally, we present the fabrication method for a stacked gate L-shaped TFET.

Effects of electrode materials on the device performances and instabilities in amorphous InGaZnO thin film transistors

The effects of electrode materials on the device performances and instabilities in amorphous InGaZnO thin film transistors (a-IGZO TFTs) have been investigated. The dependences of the source and drain resistance (RSD) and the effective channel length (Leff) on the gate biases were explained by the accumulation layer under the gate overlap (LGOV) which was formed due to the oxygen out diffusion from the channel layer. The RSD with electrode materials is determined by not only workfunction (ΦM) but the electrical property of the metal oxide formation. From the threshold voltage shifts with different electrode materials under positive gate bias stress (PBS), the more device degradation could occur when the more electrons are accumulated in LGOV.

Bias-dependent Access Resistances Extraction in 0.15 µm GaAs pHEMTs

Devices’ performance analysis and successful circuit design strongly depend on accurate large signal models. This, in turn, requires accurate small signal models. However, the reliable parasitic parameter extraction of GaAs pHEMT greatly influences the accuracy of small signal models, which also greatly influences the extraction of intrinsic elements. The access parasitic source and drain resistances, Rs and Rd, are associated with gate bias due to the two-dimensional charge control. In this work, we directly extract Rs and Rd from S-parameter measurements of the device under test (DUT) under strong inversion operating biases. The proposed method has been validated by simulation and on-wafer measurements. It shows better accuracy than existing arts in a frequency range of 0.5–40 GHz (0.5 GHz step). Furthermore, a 10-15 GHz GaAs pHEMT power amplifier (PA) is employed to further validate the developed method. The test results also validate the developed method.

A Rigorous Investigation of Electrostatic and Transport Phenomena of GaN Double-Channel HEMT

This paper presents a comprehensive investigation of electrostatics and transport characterization of GaN double-channel (DC) MOS-HEMT. Upon derivation of a polynomial analytical expression establishing a relationship between the Fermi level and the 2-D electron gas density (2DEG), a relationship between the sheet carrier density and applied gate voltage has been obtained. To confirm the validity of the model in both subthreshold and strong inversion regions, the charge density profile and capacitance–voltage profile have been attained from self-consistent simulation incorporating the quantum mechanical effect. The impact of GaN channel thickness on the conduction band profile as well as charge density profile has also been investigated. A 2-D analytical model for current–voltage characteristics of GaN-DC-MOS-HEMT has been developed for the first time. Assuming velocity saturation of electrons in 2DEG, the effects of spontaneous and piezoelectric polarization at the heterointerface, field dependent mobility, and the parasitic source and drain resistance have been taken into account in evolution of this model. The ON-resistance extracted from the analytical model was found to be 7.1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \cdot $ </tex-math></inline-formula> mm, which is in close proximity with experimental results. A steep subthreshold swing of 79 mV/dec was determined from the current–voltage characteristics with an ON– OFF drain current ratio of the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , which holds the promising application for enhancement mode operation with minimal leakage current. For corroboration, the derived results were compared with experimental data acquired from the literature, thereby enhancing the reliability of this model.

Extraction of Packaged GaN Power Transistors Parasitics Using S-Parameters

In order to better predict the high-frequency switching operation of transistors in power converters, parasitic elements of these devices such as resistances, inductances, and capacitances must be accurately evaluated. This paper reports on the characterization of a gallium nitride (GaN) packaged power transistor using S-parameters in order to extract the device parasitics. Because the transistor is packaged, a calibration technique is carried out using specific test fixtures designed on FR4 printed circuit board (PCB) in order to get the S-parameters in the transistor plane from the measurement. The proposed method is suitable for a wide range of power devices. In this paper, it is applied to an enhancement-mode GaN high electron mobility transistor (HEMT). The impact of junction temperature on drain and source resistances is also evaluated. According to characterization results, equation-based modeling is proposed for the nonlinear parameters. The extracted parasitic elements are compared with reference values given by the device manufacturer.