Drain Leakage Current Research Articles

High temperature silicon carbide MOSFETs with very low drain leakage current

Inversion mode n-channel MOSFETs have been built on (6H) silicon carbide (SiC) substrates, with thermal oxide as the gate insulator, and with channel lengths ranging from 1 to 25 µm. Drain leakage currents lower than 0.04 pA/µm channel width have been experimentally obtained at temperatures up to 400° C and Vd = 5V.

Interface trap effect on gate induced drain leakage current in submicron N-MOSFET's

An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5//spl mu/m LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress. The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of /spl Delta/I/sub d/=A exp(-B/sub u//F) with a value of B/sub u/ of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Novel charge injection transistors with heterojunction source (launcher) and drain (blocker) configurations

The results of a theoretical study of novel charge injection transistors (CHINTs) with heterojunction source and drain are presented. The proposed device structures employ a wide band-gap (with respect to the channel) material as the device source and/or drain regions, in contrast to the conventional, homojunction source (drain) CHINT structure. It is demonstrated that the spatial location of real-space transfer (RST) is strongly dependent on the initial energy of injected electrons in these devices. The introduction of source and drain heterojunctions serves for enhancing the RST effect and for the blocking electrons which constitute leakage current. Results from two-dimensional, self-consistent ensemble Monte Carlo simulations reveal that the proposed CHINTs feature increased current drive capability, reduced drain leakage current, and faster switching speed.

Off-state instabilities in thermally nitrided-oxide n-MOSFETs

The significant off-stage gate current of nitrided-oxide n-MOSFETs can be attributed to severe hot-hole injection into the gate oxide during band-to-band (B-B) tunneling due to a nitridation-induced lowering of the barrier height for hole injection. Some of the injected holes are even trapped in the gate oxide above the deep-depletion layer of the drain and thus decrease the gate-induced drain leakage (GIDL) current. A subsequent hot-electron injection into the gate oxide can neutralize these trapped holes and make the reduced GIDL current recover, even increase beyond the original value. The proposed mechanism of the GIDL degradation and recovery behaviors can be confirmed by the observed change in the ratio of the substrate to source currents, as well as by the field-distribution analysis of the gate oxide under stressing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Gate-induced drain leakage current in MOS devices

The gate-induced drain leakage current (GIDL) in typical n-channel MOSFETs is calculated for direct and indirect tunneling from the valence band to the conduction band of silicon, as well as tunneling from the conduction band minimum of silicon to the interface traps, and compared to experimental data. The results show that in silicon MOSFETs the GIDL is dominated by tunneling from the conduction band to the interface traps, and the contribution from both direct and indirect band-to-band tunneling is negligible. >

Ionizing radiation damage near CMOS transistor channel edges

Enhanced radiation damage near channel edges of n- and p-channel MOS transistors has been observed from measurements of channel resistance and gate-induced drain leakage current. Good correlation between these two types of measurements has been established. The degree of such edge effects has been found to depend strongly on the process technology. In some cases, the radiation damage near the edge plays a major role in the total device degradation, and it becomes more important as the device size reduces. A comparison has been made among transistors fabricated with standard, fluorinated, and radiation-hardened oxides. The results suggest that it is possible to minimize the radiation-induced edge effects by the use of appropriate process conditions. >

Degradation of junction leakage in devices subjected to gate oxidation in nitrous oxide (MOS transistors)

Nitrided gate oxides offer several electrical and reliability advantages over conventional oxides and also provide a good barrier against impurity diffusion. Oxidation in nitrous oxide (N/sub 2/O) has been very successful in overcoming some of the problems associated with nitridation in ammonia. The authors have observed that the extent of N/sub 2/O oxidation has a strong detrimental effect on the drain leakage current of MOS transistors in the off state. This phenomenon has been identified to be caused by an increase in the active area junction leakage current. >

Radiation effects on gate induced drain leakage current in metal oxide semiconductor transistors

The gate induced drain leakage current (Idl) of metal oxide semiconductor (MOS) transistors changes significantly when the devices are exposed to ionizing radiation. For n-channel MOS transistors, Idl decreases, whereas for p-channel devices, it increases. The change of leakage current at higher tunneling fields is proportional to the increase of hole trap density in the gate oxide region. The leakage current measurement technique is a useful tool for characterizing radiation effects in MOS transistors because at higher bias it is dependent on increase of oxide charge while independent of interface states. The annealing of trapped charges at the tunnel junction is faster than in the channel region as determined from subthreshold characteristics. The results of the thermal annealing experiment reveal that the drain current in the control region is attributed to interface state assisted tunneling.

Field dependent ionizing radiation effects in LDD-MOSFETs

The ionizing radiation effects in w-channel lightly doped drain (LDD) MOS transistors are evaluated for a wide range of gate fields applied during irradiation. Various device parameters, such as threshold voltage, transconductance, interface state density and drain leakage current are measured before and after irradiation. It is seen, that, unlike single drain devices, the maximum threshold voltage shift for LDD devices occurs with negative bias applied during irradiation. The threshold voltage shift increases with a decrease of channel length of the device. The drain leakage current decreases with irradiation and the decrease is proportional to the increase of trapped carrier density in the oxide region.

Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs

The maximum bit capacity of poly-Si loaded SRAMs is estimated, based on cell stability limits. When SRAM density increases, the voltage level of a storage node in the high state decreases more quickly because of MOS drain leakage current that flows in the poly-Si load; this can prevent regular cell operation. The poly-Si load resistance and the drain leakage current distribution are measured by using special 0.8- mu m 1-Mb SRAM test chips. The maximum bit capacity is then calculated for low-power and high-speed SRAMs. The limit is 4 Mb for low-power SRAMs and 4 Gb for high-speed SRAMs. >

Effect of sidewall spacer thickness on hot-carrier degradation of PMOS transistors

The effect of the sidewall spacer thickness on the hot-carrier degradation of sidewall-offset single drain PMOS transistors was studied. At the stress bias condition of maximum gate current, a large degradation was observed when there is no overlap between gate and drain. The trapping of a large number of electrons in the sidewall oxide spacer is attributed to this. In the off-state, PMOS transistors were degraded by electrons generated by the band-to-band tunnelling process. Transistors with no gate-to-drain overlap show little degradation at relatively low Vd, because of the small drain leakage current by band-to-band tunnelling. However, as Vd is increased and the drain leakage current reaches a certain level, the degree of degradation drastically increases. As in the case of the DC stress test at the peak gate current, this is probably a result of enhanced trapping of injected electrons in the sidewall spacer. These results suggest that there should be an overlap between gate and drain but that the overlap distance should be kept to a minimum in order to maximize the hot-carrier resistance of PMOSFETs. The single drain PMOS transistor with the optimum sidewall spacer thickness has a lifetime which is much longer than 10 years at an operation voltage of -3.3 V.

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n-MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.

Reduction of the latch effect in SOI MOSFETS by the silicidation of the source

A simple physical model is developed to assess the effect on single transistor latch voltage of carrier lifetime reduction and emitter efficiency degradation. The model predicts the efficacy of the latter mechanism and this is achieved experimentally by silicidation of the source. This has the effect of effectively placing the source ohmic contact close to the source/body metallurgical junction thus enhacing the hole component of the total current across the junction thereby reducing the emitter efficiency. In comparison to a non-silicided source, a 20% increase in breakdown voltage is achieved. Silicidation of both the source and drain regions is performed simultaneoulsy thus maintaining device symmetry and simplicity of processing. No significant degradation of drain leakage current was observed.

Gate current in OFF-state MOSFET

The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-AA or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I/sub D/ walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Leakage current degradation in n-MOSFETs due to hot-electron stress

The field-induced drain-leakage current can become significant in NMOS devices with thin gate oxides. This leakage current component is found to be more prominent in devices with gate-drain overlap and can increase considerably with hot-electron stress. A method which shows how measuring the gate voltage needed to obtain a constant leakage value of 0.1 nA can yield useful information on the interface charge trap density is discussed. >

Effects of fluorine ion implantation on metal-oxide-semiconductor devices of silicon-on-sapphire

Effects of fluorine ion implantation on electrical characteristics of metal-oxide-semiconductor (MOS) devices on silicon-on-sapphire have been investigated. The fluorine implantation generates deep acceptor levels, the nature of which is significantly affected by the sequence of the implantation and gate oxidation in device fabrication process steps. It was found that drain leakage current of fluorine-implanted MOS transistors can be reduced to about 0.1 times compared with unimplanted devices without degrading the basic electrical characteristics.

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero V G in thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.

Crystalline quality of silicon layer formed by FIPOS technology

The crystalline quality and electrical characteristics of isolated silicon layers fabricated by the FIPOS (Full Isolation by Porous Oxidized Silicon) technology have been studied. Transmission electron microscopy (TEM) was used to evaluate the crystalline quality and CMOS devices were used to determine the electrical characteristics of the isolated layers. Dislocations are generated in the isolated layers. These dislocations are caused by the thermal stresses present in the thick porous silicon layer during the oxidation process. Lowering the porous silicon density is effective in reducing the density of dislocations. The density of dislocations is two or three orders of magnitude lower than that in the silicon-on-sapphire (SOS) or in the epitaxial layer of the oxygen implanted silicon. The field effect mobility of n- and p-channel MOSFETs in the isolated silicon layer is the same as that in bulk silicon. The drain leakage currents of n- and p-channel MOSFETs are on the order of 10 -13-10 -14 A per 6.5 μm channel width. These results show that the dislocations do not degrade the electrical characteristics and that the isolated silicon layer is of high quality.

Improvement of SOS Device Performance by Solid-Phase Epitaxy

Crystalline quality in the whole region of silicon film on sapphire substrate has been improved by doubly applying solid-phase epitaxial regrowth combined with amorphization of both the silicon surface and the silicon-sapphire interface regions of SOS. Observations, by Rutherford backscattering and chemical delineation, indicate that planar defect density in the film becomes less than 1/100 of that in an as-grown film. Effective mobilities of n- and p-channel FETs in the improved film are 520 and 225 cm2/V·s, which are 1.3 times and 1.1 times larger than those in the as-grown film, respectively. A significantly reduced drain leakage current of 1.8×1012 A/50 µm for n-channel FET is obtained, whose value is about 1/100 of those in as-grown samples. The higher mobility and lower leakage current thus obtained, should be attributed to the drastic improvement of crystalline quality in the whole region of SOS by the double solid-phase epitaxy.

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7 \times 10^{-11}</tex> A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TD</inf> ) to be -2.1 V. This is attributed to the higher temperature dependence of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TD</inf> than that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.