Drain Depletion Region Research Articles

Hours-Long Transient Leakage Current in MOS Structures Induced by High Total-Ionizing-Dose

This article studies the apparition and the fast annealing of a leakage current in p- and n-MOS transistors and structures. This leakage current is observed for total ionizing doses (TIDs) of 50 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and above and anneals rapidly within the hours following the end of irradiation. An extensive set of specially designed and dedicated structures are used to study this phenomenon. In particular, the article presents the effects of the dose rate, the transistor type (n or p), the drain–source voltage, or the bias during annealing. Results show that the observed transient leakage current is an intensification followed by fast annealing of the generation current inside the drain and source depletion regions. It appears that this generation leakage current most likely originates from the creation of positive charges in the thick oxides of the devices, that is, the shallow trench isolation (STI) and the pre-metal dielectric (PMD), and it generally anneals at ambient temperature in less than 12 h after irradiation.

A modified pseudo 2D physically-based model for double-gate TFETs: Role of precise calculations of drain and source depletion regions

In this current study, a modified pseudo two-dimensional (2-D) semi-analytical model for double gate tunnel FETs (DG-TFETs) is introduced. The main regions in the DG-TFET structure are the channel and the depletion regions inside the source and the drain. In such regions, the 2-D Poisson's equation is solved by adjusting suitable boundary conditions. The source and the drain depletion region lengths are calculated precisely by an iterative technique resulting in an accurate prediction of the electrostatic potential. According to the obtained 2-D electrostatic potential, the energy band diagram could be extracted and, consequently, the minimum tunneling width is calculated. Accordingly, the model of drain current is introduced by applying Kane's tunneling model. Further, the source depletion charge and the channel charge are derived, and the terminal capacitance components are then extracted. A comparison between the proposed model and SILVACO TCAD simulations shows a satisfactory agreement that confirms the validation of the presented model robustness.

Thickness Modeling of Short-Channel Cylindrical Surrounding Double- Gate MOSFET at Strong Inversion Using Depletion Depth Analysis

Aims: The semiconductor technology has a great impact on consistent growth in the Very-Large- Scale Integrated (VLSI) devices. The transistor size has been scaled down from micron to submicron and towards the nanometer regime in the past 30 years due to technological advancements. The most reliable solid-state device is Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) but this rapid decrease in the device dimensions with the advent of Moore's law follows several problems, such as Short Channel Effects (SCE's) and Hot Carrier Effects. The channel becomes too small at short channel effects that necessitate the analysis of the optimum device designs, in particular in the operating conditions. The charge-sheet model that can quickly analyze a long-channel device, currently in the subthreshold to saturation regime without any discontinuity, turns out to be inappropriate at reduced channel size. Objectives: At the nano-scaling of the device, since the accumulation layer thickness is comparable to the device, the assumption of the channel as a thin sheet of charge vanishes. Though the depletion layers or zone are the regions of the absentia of charges mostly, the existence affects the device behavior and the channel thickness. Therefore, channel thickness modeling becomes essential at various bias conditions to define the specifics of device operation and the channel dependence of the structural parameters. In this work, the objective is to develop an analytical model and numerical analysis of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET, including the thickness, derived based on the formation of depletion depth to analyze the device performance at reducing dimensions. Methods: The analysis is built upon the device's physical and electrical parameters, such as capacitance, electric field, thickness, threshold voltage, effective channel dimensions, drain current, are considered in this research. The depletion region in a MOSFET structure accounts for the inclusion of the source and drain depletion regions, divided primarily into three separate sub-regions as a junction between the diffused source/drain and the substrate depletion under the channel and by region induced by lateral source and drain diffusion. The condition of a planar MOSFET in channel formation, i.e., for strong inversion, and when VGS &gt; VTH has been considered for this mathematical analysis. Results: The computed results of device thickness and depending parameters for a planar MOSFET and the CSDG MOSFET have been obtained. Based on this analysis, the silicon thickness of the typical CSDG MOSFET computed is 180 nm, 281 nm, and 327 nm at VDS 0.2 V, 0.8 V, and 1.2 V, respectively. The achieved results, through the thickness modeling proposed in this work, show that nanoscale CSDG MOSFET can be deployed for the improvements in the device performance and novel design modifications. Conclusion: The analysis presented in this work significantly contributes to understanding the dependence of semiconductor thickness in CSDG MOSFET and serves as a guide for future modifications in the structure for the device compactness.

Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around Nanosheet FET

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.

Study on the Charge Collection Mechanism of Single Event Transient Effect for Nano N-Channel Metal Oxide Semiconductor Field Effect Transistor

Based on the mechanism of charge collection, drift and diffusion, the influence of incident position, drain bias and incident particle LET (Linear Energy Transfer) value on the charge collection of NMOS devices is analyzed. It is found that the strongest electric field in drain depletion region is at 70 nm, and the maximum transient current is 3.43 mA. Drain bias affects the electric field in drain region. The higher drain bias is, the greater the electric field is, and the transient current is the larger of the peak value is, and the change of drain bias does not affect the diffusion current part; the larger the LET is, the larger the set current is, and the transient current peak value and collection charge increase linearly with the increase of LET. In addition, for a single transistor, the influence of the reduction of gate length on the bipolar amplification is analyzed, which is discovered that the reduction of gate length results in the aggravation of the single event effect. Therefore, the simulation results provide valuable reference for research on irradiation reliability and application of strained integrated circuit of Si Nano-scale NMOSFET.

Optimized Design of Carrier Injection Terminal for Reliable Low-Temperature Poly-Si TFTs Under Dynamic Hot-Carrier Stress

Dynamic hot-carrier (HC) degradation can be effectively suppressed in four-terminal low-temperature poly-Si (LTPS) thin film transistors (TFTs) with a carrier injection terminal. In order to enhance the reliability of the four-terminal LTPS TFTs, geometry effect of the carrier injection terminal, such as width and location, on the dynamic HC degradation is systematically studied. It shows that a wider carrier injection terminal, which provides more carriers injection, can suppress the degradation more effectively. As for the location, if the injection terminal is adjacent to the edge of the drain depletion region, which extends into the channel at the falling time of the gate voltage pulses, the four-terminal TFTs can provide the best immunity to the dynamic HC degradation. The proposed optimization scheme can greatly enhance the reliability of LTPS TFTs, and the mechanism can be understood based on the nonequilibrium p-n junction degradation model.

Modeling of Fringing Capacitances of Ion-Implanted Double-Gate Junctionless FETs Using Conformal Mapping

This article reports an analysis of the fringing capacitances of an ion-implanted double-gate (DG) junctionless (JL) field-effect transistors (FETs). The actual nonintegrable Gaussian function of the ion-implanted channel has been replaced by an integrable Gaussian-like vertical channel doping profile to model the fringing capacitances of the DG JLFET. The boundary conditions for the source and drain depletion regions of the uniformly doped channel has been modified according to the nonuniformly doped channel using the conformal mapping technique. In this method, the gate-oxide capacitance is transformed to the source and drain fringing capacitances using an empirical multiple coefficient ${m}$ whose value is determined by matching the model result with the ATLAS TCAD simulation data for their best fitting. It is shown that unlike the uniformly doped device, the fringing capacitances are different for the front and back gates. Furthermore, the nonlinear bias-dependent potential profile along the channel leads to different fringing capacitances at the source and drain of the proposed device. The dependence of the fringing capacitances (and ${m}$ ) on the doping profile and bias conditions are investigated in detail. Accordingly, analytical expressions for the fringing capacitances are extracted. The model results are verified by the TCAD simulations.

Design of Transistors Using High-Permittivity Materials

The design and modeling of dielectric superjunction transistors using combinations of ultrahigh permittivity materials and high-mobility materials are described. We show that placing high dielectric permittivity materials in the gate–drain depletion region can reduce electric field variations by screening the field due to depleted charges. This enables simultaneously high sheet charge density and breakdown voltage for scaled field-effect transistors. Using detailed 2-D device simulation of dc and high frequency characteristics, we show that extreme dielectric constant engineering provides unique opportunities for transistor design and has the potential to perform better than state-of-the-art millimeter-wave and terahertz frequency transistors.

TCAD Analysis of the Four-Terminal Poly-Si TFTs on Suppression Mechanisms of the DC and AC Hot-Carrier Degradation

Four-terminal poly-Si thin-film transistors (TFTs), with a counter-doped body terminal connected to the floating channel, can suppress both dc and dynamic hot-carrier (HC) degradation of TFTs. With 3-D TCAD simulation, we clarify the underlying mechanisms of the suppression effect and analyze its dependence on the position and width of the body terminal. Under dc HC condition, a wider body terminal or that closer to the drain collects more holes generated from impact ionization in the drain depletion region and suppresses the parasitic bipolar junction transistor effect, subsequently reduces the kink current more effectively. Under dynamic HC condition, the body terminal injects holes at the end of the falling time of the gate pulse, partially removes the non-equilibrium state, significantly relieves the transient maximum electric field in the drain depletion region, thus suppresses the dynamic HC degradation. A wider body terminal can inject more holes and the holes injected by that closer to the drain diffuse to drain depletion region first, thus suppress the dynamic HC degradation better.

3D numerical simulations of single-event transient effects in SOI FinFETs

The characteristics and mechanism of single-event transients in silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) were analyzed using Sentaurus technology computer-aided design (TCAD) simulations based on the bipolar amplification effect. The results show that a typical single pulse mode of the transient leakage current is observed. The peak current and collected charge increase approximately linearly with increase of the linear energy transfer. The electric field in the depletion region of the FinFET body–drain junction increases significantly when the drain bias increases, resulting in a sharp increase in the drift current until reaching the saturation state. The variation of the bipolar gain and transient current with the position of incidence of the particle shows good consistency, reaching a maximum in the FinFET drain region, which indicates that the drain depletion region of SOI FinFETs is most sensitive to heavy-ion irradiation due to the bipolar amplification effect. The bipolar gain increases with decrease of the gate length and increase of the fin height and width.

2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effect

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator.

Reduction of TFET OFF-Current and Subthreshold Swing by Lightly Doped Drain

This brief models the effect of lightly doped drain on the $I_{\mathrm { {ds}}}$ – $V_{\mathrm { {gs}}}$ and $I_{\mathrm { {ds}}}$ – $V_{\mathrm { {ds}}}$ characteristics of tunnel FETs. It is shown that an extended drain depletion region can greatly reduce both the off-current and the subthreshold swing with essentially no impact on the on-current. In particular, a lightly doped drain mitigates the undesirable ambipolar effect that cannot otherwise be relieved by lengthening the channel length. However, if the density of states is not sufficiently low, a low drain doping could result in a nondegenerate condition in which the tunneling window is blocked at $V_{\mathrm { {ds}}} = 0$ , degrading the linear region current.

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate---gate charge coupling is investigated at pillar thicknesses in the range of 200---10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60---120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate---gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate---gate charge coupling.

Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs

In this paper, a new 2-D analytical model for the surface potential of a dual-metal-gate double-gate tunnel field-effect transistor is presented. It takes into account the effects of the drain and gate voltages, gate metal work function, insulator thickness, silicon film thickness, and source and drain depletions. The surface potential thus obtained is used to calculate the tunneling widths at both the source and drain junctions, which are subsequently used as the limits for the integration of the band-to-band generation rate in order to arrive at the tunneling current. In this paper, the band-to-band tunneling is considered to take place through both the source as well as the drain depletion regions. Our model accounts for the variable drain doping through a fitting function, which is postulated based on the theory of generation current, and the results have been found to predict the correct ambipolar behavior of the tunneling field-effect transistors. The results of our model, both for the surface potential and the tunneling current, match very well with those obtained through the TCAD simulations.

Calculating drain delay in high electron mobility transistors

An expression for the signal delay (drain delay) associated with electrons traveling through the gate–drain depletion region has been obtained for nonuniform electron velocity. Due to the presence of the gate metal, the signal delay through the gate–drain depletion region was shown to be larger than the signal delay in the base–collector depletion region of a bipolar transistor when equal depletion lengths and velocity profiles were assumed. Drain delay is also shown to be larger in transistors with field plates (independent of field plate connection) compared to transistors without field plates when equal depletion lengths and velocity profiles were assumed. For the case of constant velocity, two expressions for the proportionality constant relating drain delay and electron transit time across the depletion were obtained.

Negative Gate Transconductance in MIS Tunnel Diode Induced by Peripheral Minority Carrier Control Mechanism

Negative gate transconductance (NGT) has been demonstrated in various devices like gated resonant tunneling devices, modulation doped FETs, and gate/source overlapped heterojunction tunnel FETs, and has been used for ultra-high frequency filters, multi-level logics, and phase encoder applications. [1] In this work, NGT is also observed in a metal-insulator-semiconductor (MIS) tunnel diode. The current of an MIS tunnel diode is very sensitive to surrounding signals. Therefore, MIS tunnel diodes have been used as solar cells and sensing devices. It was found that the saturation current of the MIS tunnel diode is mainly flowing along the edge of the device due to the fringing field effect. [2] Also, it was found that the saturation current increases with oxide thickness. [3] It was believed that the saturation current is dominated by the Schottky diode reverse­­­-bias current, the thicker the oxide, the lower the effective Schottky barrier height, and therefore the current is larger. In previous studies [3], it was also observed that the saturation current of the MIS tunnel diode may increase with increasing light intensity or temperature. It was attributed to that the light or temperature would change the minority carriers distribution profile at the fringe of the device. The lateral diffusion current of minority carriers is therefore changed, which affects the effective Schottky barrier height and the current at device edge. In this work, the edge Schottky diode current of an MIS tunnel diode, Al/2.2 nm SiO2/Si(p), controlled by the gate voltage of a nearby MIS tunnel gate capacitor (with the same structure as the MIS tunnel diode, but it functions as a gate capacitor with ultra-thin oxide) is demonstrated. Figure 1 shows the schematic diagrams of the fabricated MIS tunnel diode (the inner circle device) with an MIS tunnel gate capacitor (the ring device) nearby. Figure 2(a) shows the measured MIS tunnel diode saturation currents (ID ) versus the gate voltages of the MIS tunnel gate capacitor (VG ). NGT in ID is observed. Note that the valley of the kink matches the flat-band region of the MIS tunnel gate capacitor. Figure 2(b) shows the TCAD simulation of the electron concentration at the gate edge, ngap (x=0), versus VG while VD =3 V. Similar behavior to NGT is also observed, which evokes the correlation between the ngap and ID . Figure 3 shows the schematic diagrams of the mechanism of how VG affects ID . Note that larger gradient of ngap at drain depletion region edge (x=S *) leads to larger lateral diffusion flux of electrons, F e-, which lowers the effective Schottky barrier height of holes, φ h , at the edge of MIS tunnel diode, and increases ID (≈Ih , the Schottky diode current of holes). In short, ID increases with the gradient of ngap (x=S *). The gradient of ngap (x=S *) is changed as follows: (a) While VG is in accumulation region, the gate electrons (ninj ) inject into the Si substrate due to the quantum tunneling effect, which increases the ngap (x=0) and the gradient of ngap . (b) While VG is in flat-band region, the electron injection decreases due to the lower electric field, which decreases the ngap (x=0) and the gradient of ngap . (c) While VG is in depletion region, the depletion region comes out and the inversion charge, ninv , rises, which increases the gradient of ngap . (d) While biasing VG further positive, the electrons at the gap are attracted toward the gate by the substrate electric field at gate edge, ε s,edge , and then the electrons tunnel to the gate metal, which decreases the ngap (x=Wdep ) and the gradient of ngap . The NGT mechanism in ID is therefore concluded. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031. Figure Captions: Figure 1. Schematic diagrams of the fabricated device structure. Figure 2. (a) MIS tunnel diode saturation currents (ID ) versus the gate voltages of the MIS tunnel gate capacitor (VG ). (b) TCAD simulation of the electron concentration at the gate edge, ngap (x=0), versus VG while VD =3 V. Figure 3. Schematic diagrams of the mechanism of how VG affects ID (≈Ih ), as VG is in (a) accumulation, (b) flat-band, (c) depletion, and (d) deep depletion regions. The values of VFB , VG 1, and VG 2are shown in Figure 2(a).

A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling

In this paper, a 2-D analytical model for the drain current of a dual material gate tunneling field-effect transistor is developed incorporating the effects of source and drain depletion regions. The model can forecast the effects of drain voltage, gate work function, oxide thickness, and silicon film thickness. The proposed model gives analytical expressions for the surface potential, electric field and the band to band generation rate which is numerically integrated to give the drain current. More importantly, our model accurately predicts the ambipolar current and the effects of drain voltage in the saturation region. A semi-empirical approach is used to model the transition from the linear to the saturation region, leading to an infinitely differentiable characteristics. The model is shown to be scalable down to a gate length of 50 nm. The model validation is carried out by a comparison with 2-D numerical simulations.

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (VT) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the VT value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90nm) and being fabricated using the low threshold voltage (low-VT) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-VT and high-VT ones. Abnormally large values of DIBL were found for low VT-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-VT process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L=60nm fabricated using the low-VT process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.

Spherical 구조를 갖는 고전압용 Analog CMOS의 Drain 역방향 항복전압의 계산 방법

A calculation method of the breakdown voltage for the Drain region with the spherical structure in high voltage analog CMOS is proposed. The Drain depletion region is divided into many sub-regions and the doping concentration of each sub-region is assumed to be constant. The field in each sub-region is calculated by the integration of the net charge and the breakdown voltage is calculated using the ionization integral method. The breakdown voltage calculated using the proposed method shows the maximum relative error of 3.3% compared with the result of the 2-dimensional device simulation using BANDIS.

Degradation of the front and back channels in a deep submicron partially depleted SOI NMOSFET under off-state stress

The hot-carrier effect characteristic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress. The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device. The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel. At low gate voltage, there is a hump in the sub-threshold curve of the back gate transistor, and it does not shift in the same way as the main transistor under stress. While under the same condition, there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.