Abstract
This article reports an analysis of the fringing capacitances of an ion-implanted double-gate (DG) junctionless (JL) field-effect transistors (FETs). The actual nonintegrable Gaussian function of the ion-implanted channel has been replaced by an integrable Gaussian-like vertical channel doping profile to model the fringing capacitances of the DG JLFET. The boundary conditions for the source and drain depletion regions of the uniformly doped channel has been modified according to the nonuniformly doped channel using the conformal mapping technique. In this method, the gate-oxide capacitance is transformed to the source and drain fringing capacitances using an empirical multiple coefficient ${m}$ whose value is determined by matching the model result with the ATLAS TCAD simulation data for their best fitting. It is shown that unlike the uniformly doped device, the fringing capacitances are different for the front and back gates. Furthermore, the nonlinear bias-dependent potential profile along the channel leads to different fringing capacitances at the source and drain of the proposed device. The dependence of the fringing capacitances (and ${m}$ ) on the doping profile and bias conditions are investigated in detail. Accordingly, analytical expressions for the fringing capacitances are extracted. The model results are verified by the TCAD simulations.
Published Version
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