Drain Current Noise Spectral Density Research Articles

Impact of source/drain lateral straggle on GIDL current of low SS NC-FinFET

ABSTRACT In this paper, the gate-induced drain leakage (GIDL) issue in negative capacitance (NC-FinFET) has been comprehensively addressed using Sentaurus 3-D TCAD simulations. Incorporation of ferroelectric (FE) materials in the gate stack of NC-FinFET increases with current by 12% compared to that of baseline FinFET. A steeper sub-threshold swing (SS) of 8 mV/dec is achieved at a FE-thickness of 5 nm at a lateral straggle; (σ) = 0 nm. GIDL behaviour with respect to the variation of source/drain σ and gate oxide thicknesses of NC-FinFET with and without the presence of the GateTunneling model is thoroughly investigated. Investigations demonstrate that in NC-FinFET, there are steeper energy band profiles near source/drain owing to coupling of fringing fields to the ferroelectric layer, which exhibits a larger and prior commencement of the longitudinal band to band tunnelling current compared to conventional FinFET. Moreover, the effect of variation of σ on various parameters viz. SS, capacitance and transconductance has also been investigated, which shows better results for lower σ values. At σ = 0 nm, drain-induced barrier lowering is −187.23 mV/V as compared to that of σ = 5 nm, which is −355.3 mV/V. Furthermore, we have also investigated drain current noise spectral density (SID) and gate voltage noise spectral density (SVG) with respect to fin width (WFIN) at the optimised σ value.

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

The effect of high- and low-temperature conditions on the performance of IGZO TFT and logic circuits were investigated in this work. In the temperature range of 250−350 K, the performance of the IGZO TFT did not show significant changes and exhibited a certain degree of high- and low-temperature resistance. When the temperature was below 250 K, as the temperature decreased, the threshold voltage (VTH) of the IGZO TFT significantly increased, the field effect mobility (μFE) and the on state current (ION) significantly decreased. This is attributed to the lower excitation degree of charge carriers at extremely low temperatures, resulting in fewer charge carriers transitioning to the conduction or valence bands, and the formation of defects also limits carrier migration. When the temperature exceeded 350 K, as the temperature increased, more electrons could escape from the bandgap trap state and become free charge carriers, and the IGZO layer was thermally excited to produce more oxygen vacancies, resulting in higher μFE and lower VTH. In addition, the drain current noise spectral density of IGZO TFT conformed to the 1/ƒ noise characteristic, and the degradation mechanism of IGZO TFT over a wide temperature range was confirmed based on the changes in noise spectral density at different temperatures. In addition, an inverter logic unit circuit was designed based on IGZO TFT, and the performance changes over a wide temperature range were analyzed. This lays the foundation for IGZO TFT to be applied in integrated circuits with harsh environments.

Analysis of noise behavior and reliability of pocket doped negative capacitance FET under the impact of trap charges and temperature

This paper represents an in-depth investigation of low to high frequency noise performance of highly doped double pocket double gate NCFET (HDDP-DG-NCFET) and single gate NCFET (SG-NCFET) in the existence of Uniform and Gaussian trap charges at various frequencies and temperatures (200 K–400 K). The drain current noise spectral density (Sid) and Gate voltage noise spectral density (Svg) at different frequencies in existence of both type of trap charges are explored. In addition, the Sid as a function of frequency for various ferroelectric thicknesses (Tfe) is examined in the existence of Uniform trap charges. The findings show that, at lower frequencies flicker noise dominates, while at higher frequencies, the dominant noise element is diffusion noise. For the whole range of considered frequencies, the Generation-Recombination (G-R) noise is more substantial in existence of trap charges. It has been found that, the net Sid value of the HDDP-DG-NCFET for Uniform and Gaussian types of trap distribution is 6.98 × 10−14A2/Hz and 6.17 × 10−14A2/Hz, respectively. Moreover, the examination of Sid for various Tfe in presence of traps illustrates the significance of the ferroelectric layer in obtaining lower value of net Sid, particularly in the higher frequency region and the minimal net Sid value for Tfe = 7 nm as compared to other Tfe values. Finally, to examine the device's reliability, the temperature investigation for the noise in the non-existence and existence of trap charges demonstrates that, the impact of an increase in noise caused by the existence of trap charges is much pronounced at lower temperatures and smaller gate voltages, where G-R noise is observed to be the dominant noise component.

Impact of Gaussian Traps on the Characteristics of L-shaped Tunnel Field-effect Transistor

Background: Internet of Things (IoT) applications require high-performance TFET devices that can be efficiently integrated with the cyber world and physical world. Objectives: The impact of introducing Gaussian traps in hetero-junction tunneling-field-effecttransistors (TFET) with an L-shaped gate is presented. Methods: The 2-D TCAD study of different characteristics, like input, output characteristics, and noise spectral density with trap and without trap, has been performed. Results: The simulation results showed that in L-shaped TFET (L_TFET), the high on-current of 1.93×10-5 A/μm, low off-current/leakage current of 1.09×10-13 A/μm, and steep sub-threshold slope (SS) of 24 mV/dec without traps and on-current of 8.46×10-6 A/μm, off-current of 2.86×10- 11 A/μm, and degraded SS with traps are observed. They also indicated that the presence of traps reduces gate-drain capacitance (Cgd), while gate-source capacitance (Cgs) remains unaffected. In addition, in L_TFET, the drain current noise spectral density (SID) of 7.63 E-21 (A2/Hz) at LF and 2.69 E-26 (A2/Hz) at HF while the noise voltage spectral density (SVG) of 7.33 E-4 (V2/Hz) at LF and 2.59 E-15 (V2/Hz) at HF without traps have been investigated in this study. The inverse dependence of drain current noise spectral density on frequency has been observed to lower the effect of noise at HF. Conclusion: It can be concluded that the proposed L_TFET device is free from ambipolarity conduction and can be well-suited for low-power applications.

Triboelectric-potential configurable MoTe2 homojunction for photovoltaic device and logic circuits

Reconfigurable devices based on two-dimensional materials are considered as one of the ways to extend Moore's Law. However, most reconfigurable devices use a gate voltage to dope the channel electrostatically, and the continuously applied gate voltage poses the problem of high device power consumption. Here, for the first time, we propose a tribotronic reconfigurable MoTe2 field effect transistor, where the power consumption of the device is greatly reduced by using triboelectric potentials generated by external mechanical operations instead of applying gate voltages. The drain current noise spectral density test proves that no additional current noise interferes with the output current during mechanical operation. Mechanical operation allows facile modulation of four different channel polarities (n-n, p-p, p-n, and n-p) in a single transistor. We demonstrate the potential application of a tribotronic p-n diode for photovoltaic device. The logic circuit composed of two tribotronic reconfigurable transistors realizes the logic functions of inverter, AND gate, and OR gate. Our device extends tribotronic logic and demonstrates great potential for human-machine interaction, intelligent sensors, and wearable devices.

Noise behavior of vertical tunnel FETs under the influence of interface trap states

A detailed analysis of low frequency noise behavior of two different vertical TFETs namely n ​+ ​pocket VTFET and dual MOS capacitor (D-MOS) VTFET is presented in this work. Such analysis is performed to understand the limiting factors of their operations. The effect of the presence of both uniform and Gaussian type of interface trap charge distributions on the electrical performance of the devices under consideration are considered in the TCAD simulation study. The results report that the Flicker noise is dominant at low frequency whereas at high frequency, the diffusion noise is the superior noise component. The generation-recombination noise is found to be significant in the entire frequency range considered for the analysis. Lastly, comparison has been done on net drain current noise spectral density (Sid) of some published work and this work.

Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs

In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.

Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true noises

This paper reports the investigation of conventional junctionless tunnel FET (JL-TFET) and N+ pocket-doped junctionless vertical tunnel FET (JL-VTFET). The investigation is done by analyzing the effect on the ID–VGS characteristics (a) under a wide range of temperature and (b) in the presence of acceptor interface trap charges. This work also examines the performance of noise and its impact on the digital inverter. Comparison has been made on the TCAD simulated results of both the devices. It is observed that the degradation of drain current (ID) is less in JL-VTFET and also it has better noise performance than that of conventional JL-TFET. Its net drain current noise spectral density (Sid) reaches 10–15 A2/Hz till 1 MHz and decreases with further increase in frequency. The contributions of generation–recombination noise and flicker noise are found to be more in low and moderate frequency, whereas diffusion noise dominates at high frequency. Furthermore, the impact of interface traps is studied using complementary JL-VTFET digital inverter application and compared with the one without interface traps. The transient characteristics show an average delay of 15 ps and 27 ps in the absence and presence of interface traps, respectively.

Correlation between border traps and exposed surface properties in gate recessed normally-off Al2O3/GaN MOSFET

We report the effect of the gate recess process and the surface of as-etched GaN on the gate oxide quality and first reveal the correlation between border traps and exposed surface properties in normally-off Al2O3/GaN MOSFET. The inductively coupled plasma (ICP) dry etching gate recess with large damage presents a rough and active surface that is prone to form detrimental GaxO validated by atomic force microscopy and X-ray photoelectron spectroscopy. Lower drain current noise spectral density of the 1/f form and less dispersive ac transconductance are observed in GaN MOSFETs fabricated with oxygen assisted wet etching compared with devices based on ICP dry etching. One decade lower density of border traps is extracted in devices with wet etching according to the carrier number fluctuation model, which is consistent with the result from the ac transconductance method. Both methods show that the density of border traps is skewed towards the interface, indicating that GaxO is of higher trap density than the bulk gate oxide. GaxO located close to the interface is the major location of border traps. The damage-free oxidation assisted wet etching gate recess technique presents a relatively smooth and stable surface, resulting in lower border trap density, which would lead to better MOS channel quality and improved device reliability.

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. The study has been performed for devices with different channel lengths and doping concentrations biased close to the threshold and deep in linear regime. It has been shown that the surface potential of JNTs is strongly influenced by the substrate bias even above threshold. Thus, the drain current noise spectral density and the effective trap density can be improved or degraded depending on the bias applied to the substrate of the devices. Additionally, it is shown that, the variation on the substrate bias enables the evaluation of traps with different activation energy ranges, which is more evident in heavier doped devices due to the higher threshold voltage sensitivity to the substrate bias.

High-Performance Poly-Si TFTs Using Ultrathin $\hbox{HfSiO}_{x}$ Gate Dielectric for Monolithic Three-Dimensional Integrated Circuits and System on Glass Applications

High-performance poly-Si thin-film transistors (TFTs) using an ultrathin high- κ metal gate stack with a subthreshold swing (SS) of 193 mV/dec when operating at room temperature and maximum thermal budget of 700°C are readily compatible with monolithic 3-D integrated circuits (3D-ICs) and silicon-on-glass (SOG) applications. The SS is reduced to 31 mV/dec, and the on/off current ratio is increased to 108 at 77 K; the result is a significant reduction of leakage current and lower power consumption. Long-channel TFTs have a higher drain current noise spectral density SID and a smaller exponential frequency factor (γ) due to the influence of numerous grain boundaries on carrier transport, as confirmed by gap state density extraction. These devices may pave the way for high-performance circuit designs and applications, such as monolithic 3D-ICs, SOG, and active-matrix organic LED.

Thermal dependence of low-frequency noise in polysilicon thin film transistors

Thermal dependence of low frequency noise in low temperature (≤ 600 °C) polysilicon thin film transistors is studied in devices biased from weak to moderate inversion and operating in the linear mode. Drain current noise spectral density, measured in the temperature range from 260 K to 310 K, is thermally activated following the Meyer Neldel rule. Analysis of the thermal activation of noise, supported by the theory of trapping/detrapping processes of carriers into oxide traps located close to the interface, leads to the calculation of the deep state interface distribution in function of the Meyer Neldel characteristic energy.

A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs

This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub -100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> . This paper may provide insights for analog design using advanced strained devices.

Origin of the front-back-gate coupling in partially depleted and fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors with accumulated back gate

It is shown that in thin-gate partially depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors (PD SOI MOSFETs) unexpected front-back-gate coupling effects occur when the back gate is operated in accumulation. This is particularly true for front-gate biases (VGF) beyond the threshold for electron valence-band tunneling to occur, inducing the so-called linear kink effect (LKE). As a consequence of this coupling, both the drain current and the drain-current noise spectral density are reduced in the LKE regime. Moreover, for a back-gate bias into stronger accumulation, the LKE regime is shifted to higher VGF in absolute value. Another consequence of the front-back-gate coupling is the appearance of the back-gate-induced (BGI) Lorentzian component in the noise spectra measured for an accumulated back gate in a wide range of VGF. Similar effects have also been detected in thin-gate fully depleted SOI MOSFETs. It is demonstrated that all these front-back coupling effects can be explained by considering the increased body-source leakage currents and, hence, the body-source conductance induced by the accumulation back-gate voltage where the BGI Lorentzian is attributed to the Nyquist noise in the back-gate-induced body-source conductance affected by the capacitive character of the body-source impedance.

High-energy proton irradiation induced changes in the linear-kink noise overshoot of 0.10 μm partially depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors

This article describes the impact of a high-energy proton irradiation on the parameters of the Lorentzian noise overshoot, occurring in ultrathin gate oxide 0.10 μm partially depleted (PD) silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs), operated in the linear regime. It is shown that the drain current noise spectral density SI exhibits an increase after irradiation, while the Lorentzian time constant τ shows a different response to the 60/65 MeV protons in n- or p-channel transistors. In addition, the excess noise peak develops a pronounced radiation-induced dependence on the back-gate bias VBG, which is different for both device types: a strong increase of SI is found for the PD SOI p-MOSFETs, upon changing VBG into the accumulation regime, while in the first instance, the opposite is found for the n-MOSFETs. These observations are discussed in terms of a RC-filtered shot noise model and of the ionization induced positive charge trapping in the buried and isolation oxides. The results lead to the conclusion that in n-MOSFETs, an additional generation-recombination component becomes active by the charge trapping. In the p-type counterparts, on the other hand, it is believed that irradiation modulates the body-channel coupling factor, giving rise to a strong increase of SI with VBG, while the corresponding τ is in a first approximation not affected.

Hot-carrier-induced degradation in short p-channel nonhydrogenated polysilicon thin-film transistors

The effects of low gate voltage |V/sub g/| stress (V/sub g/=-2.5 V, V/sub d/=-12 V) and high gate voltage |V/sub g/| stress (V/sub g/=V/sub d/=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V/sub g/| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V/sub g/| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds.

Empirical relationship between low-frequency drain current noise and grain-boundary potential barrier height in high-temperature-processed polycrystalline silicon thin-film transistors

The relationship between low-frequency drain current noise spectral density SI and grain-boundary potential barrier height Vb is investigated in high-temperature-processed polycrystalline silicon thin-film transistors. It is demonstrated that a general empirical relationship exists between SI and Vb indicating that the noise sources are located at the grain boundaries. The implications of the obtained relationship between SI and Vb from the practical viewpoint are discussed.

A new 1/f noise model for metal-oxide-semiconductor field-effect transistors in saturation and deep saturation

A new 1/f noise model for metal-oxide-semiconductor field-effect transistors (MOSFETs) in saturation and deep saturation based on the Hooge’s mobility fluctuation (MF) noise expression is presented. The new model uses detailed one-dimensional expressions of carrier number per unit length n(x) and channel potential V(x) varying with channel position x to calculate the gate referred noise spectral density SVG(f) in both saturation and deep saturation. The analytic variation of both n(x) and V(x) with x has been corroborated with a two-dimensional device simulator. In addition, new formulas for 1/f noise in MOSFETs based on the number fluctuation (NF) model are also presented. The theoretical results of SVG(f) and the drain current noise spectral density SID(f) versus biasing voltages, using the MF model, are in better agreement to the experimental results than the theoretical results of SVG(f) and SID(f) based on the NF model.