Double-trench MOSFET Research Articles

SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-Low Power Loss and Improved Short-Circuit Capability

SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-Low Power Loss and Improved Short-Circuit Capability

A Novel 4H-SiC Asymmetric MOSFET with Step Trench.

In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (Cgd) to the gate-to-source capacitance (Cgs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and deep double-trench MOSFET (DDT-MOS), is demonstrated to have an increase of 200 V and 50 V in the breakdown voltage (BV), decreases of 21.8% and 10% in the specific on-resistance (Ron,sp), a reduction of about 1 V in the induced crosstalk voltage, and lower switching loss. Additionally, the trade-off between the resistance of the JFET region (RJFET) and the electric field in the gate oxide (Eox) is studied for a step trench and a deep trench. The improved performances suggest that a step trench is a competitive option in advanced device design.

Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed.

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate-drain capacitance (Cgd) and gate-drain charge (Qgd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater Ron,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique.

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure.

A Novel 4H-SiC Double Trench MOSFET with Built-In MOS Channel Diode for Improved Switching Performance

This study proposed a novel 4H-SiC double trench metal-oxide-semiconductor field-effect-transistor (DTMCD-MOSFET) structure with a built-in MOS channel diode. Further, its characteristics were analyzed using TCAD simulation. The DTMCD-MOSFET comprised active and dummy gates that were divided horizontally; the channel diode operated through the dummy gate and the p-base and N+ source regions at the bottom of the dummy gate. Because the bult-in channel diode was positioned at the bottom, the DTMCD-MOSEFT minimized static deterioration. Despite having a 5.2% higher specific on-resistance (Ron-sp) than a double-trench MOSFET (DT-MOSFET), the DTMCD-MOSFET exhibited a significantly superior body diode and switching properties. In comparison to the DT-MOSFET, its turn-on voltage (VF) and reverse recovery charge (Qrr) were decreased by 27.2 and 30.2%, respectively, and the parasitic gate-drain capacitance (Crss) was improved by 89.4%. Thus, compared with the DT-MOSFET, the total switching energy loss (Etot) was reduced by 41.4%.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

Heavy-ion induced gate damage and thermal destruction in double-trench SiC MOSFETs

This article presents the experimental results of the heavy-ion-induced gate oxide damage and single-event burnout (SEB) in 1200 V SiC double-trench MOSFETs. The short-circuit between any two terminals of devices under test (DUTs) was observed during the exposure with a drain bias of only 100 V and post-irradiation measurements. In addition, the experimental results also showed that the SEB threshold of DUTs does not exceed 500 V, which was lower than 42 % of the rated breakdown voltage. TCAD simulations revealed that the electric field concentrated at the corner and sidewall of gate oxide, resulting in the latent oxide damage, which should be responsible for the leakage current degradation at low drain bias. It was also verified that the SEB failure was due to the thermal destruction caused by the high temperature near the n− drift/n+ substrate junction, which was further determined by the SEM image of the die surface. The findings in this article could provide indications for future use of such state-of-the-art SiC double-trench MOSFETs in space.

A 4H–SiC double trench MOSFET with split gate and integrated MPS diode

A 4H–SiC double trench MOSFET with split gate and integrated MPS(Merged PiN Schottky) diode (MPS-SGMOS) is proposed, and simulated by Sentaurus TCAD tools. The introduction of the P+ shielding region ensures the reliability of the gate oxide of the device, reduces the electric lines of force gathered at the bottom of the gate oxide, and improves the withstand voltage of the device; the introduction of the Schottky diode enables the device to obtain better reverse recovery performance; adding a source electrode between the split gate reduces the Cgd greatly and the switching losses of the device, so that the device is more suitable for high frequency applications. As a result, comparing to conventional double-trench MOSFET (Con-DTMOS), MPS-SGMOS owns comparable on-state characteristics, while its breakdown voltage is increased by 10.5%. The FOM(figure of merit) of Ron,sp × Qgd, sp is decreased by 78.2% compared to the traditional device, moreover the peak reverse recovery charge is decreased by 32.7%.

A Novel SiC MOSFET With a Fully Depleted P-Base MOS-Channel Diode for Enhanced Third Quadrant Performance

In this article, a novel silicon carbide double-trench MOSFET with an integrated fully depleted P-base MOS-channel diode is proposed and investigated by calibrated TCAD simulations. The proposed silicon carbide (SiC) MOSFET features a fully depleted P-base region achieved by shrinking the source trench mesa in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${z}$ </tex-math></inline-formula> -direction. Due to the significantly reduced conduction band energy in the fully depleted P-base region, a low potential barrier for electrons to flow through the JFET region to the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> source region is formed. As a result, the proposed SiC MOSFET not only exhibits more than three times lower diode cut-in voltage than the body p-i-n diode but also successfully eliminates the bipolar degradation issues. Besides, a compact model based on Poisson’s law is developed to understand the origin of the barrier lowering effect. Calibrated TCAD simulation results indicate that the enhanced third quadrant performance would not comprise the other electric characteristics, which makes the proposed SiC MOSFET a highly promising candidate for high-frequency power applications.

Degradation of 650 V SiC double-trench MOSFETs under repetitive overcurrent switching stress

In this paper, the ruggedness of 650 V SiC double–trench MOSFETs (DT-MOS) under repetitive overcurrent switching stress was evaluated and investigated experimentally. The devices under test (DUTs) were electrically stressed by the hard switching transient as well as the conduction current nearly four times the rated one. It was shown that the threshold voltage (VTH) and on-resistance (RON) of DUTs increased after 100 K stress cycles, indicating the occurrence of performance deterioration. TCAD simulations revealed a similar failure mechanism with HTGB that the electrons injection into the gate oxide during the conduction stage should take the responsibility, which is totally different from the case of SiC planar-gate ones. What's more, the dependence of such degradation on the conduction duration TCD, overcurrent level IOL, driving condition VGS(ON/OFF) and gate resistors RG(ON/OFF) was researched comprehensively. The findings in this paper could provide indications to better drive such state-of-the-art SiC DT-MOS for long-term use in power electronic applications.

High performance 4H-SiC MOSFET with deep source trench

In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s figure of merit of DST-MOSFET improved by 9% and 104%, respectively, in comparison with those of UMOSFET; and by 37% and 64%, respectively, compared to those of DT-MOSFET. Additionally, the SPR reduced the gate-to-drain capacitance of the DST-MOSFET and improved the switching characteristics. Consequently, the total switching energy loss of the proposed DST-MOSFET reduced by 63% and 47% in comparison with those of the UMOSFET and DT-MOSFET, respectively.

Impact of Negative Gate Bias and Inductive Load on the Single-Pulse Avalanche Capability of 1200-V SiC Trench MOSFETs

In this study, the single-pulse avalanche capability of two types of 1.2-kV silicon carbide (SiC) trench MOSFETs was investigated through unclamped inductive switching (UIS) testing and numerical TCAD simulation. It was found that the UIS failure mechanisms differed in the two MOSFETs. In the asymmetric trench MOSFET, the failure was caused by high temperature, which can damage the SiC layer during the UIS transient, whereas in the double-trench MOSFET, the failure was caused by a high electric field concentration at the trench gate bottom oxide, and the physical damage was confirmed by optical beam induced resistance change (OBIRCH) and scanning electron microscopy (SEM) cross-sectional analysis. In addition, the UIS-based local damage phenomenon was investigated with varying inductance. Nonuniform contact resistance may have been a cause of the avalanche current concentration.

Investigation of SiC Trench MOSFETs' Reliability under Short-Circuit Conditions.

In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure.

Crosstalk Induced Shoot-Through in BTI-Stressed Symmetrical &amp; Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, the crosstalk-induced shoot-through current and induced gate voltage of SiC planar MOSFETs, SiC symmetrical double-trench MOSFETs and SiC asymmetrical double-trench MOSFETs is investigated on a half-bridge circuit to analyse the impact of temperature, drain-source voltage switching rate, gate resistance and load current level on crosstalk-induced properties of different SiC MOSFET structures. It shows that due to the smaller gate-source capacitance, the two double-trench MOSFETs exhibit higher induced gate voltage during crosstalk with the same external gate resistance, which together with the higher transconductance, yield higher shoot-through current than the planar MOSFET. Accordingly, their shoot-through current decreases with increasing of the load current while the planar MOSFET exhibits an opposite trend. The different trend of shoot-through current with temperature on DUTs reveals that the crosstalk in different device structures are dominated by different mechanisms, i.e. threshold voltage and channel mobility with the gate-source capacitance influencing the amplitude. Impact of bias temperature instability with positive and negative gate stressing is measured with a range of stress and recover periods at temperateness ranging between 25 °C to 175 °C. These measurements show that the peak shoot-through correlates with the threshold drift, though with less sensitivity for SiC symmetrical and asymmetrical double-trench MOSFETs compared with the planar SiC MOSFET where the inter-dependence is pronounced. A model is developed for the induced gate voltage and shoot-through current during crosstalk with channel current considered. The comparison of the model results with measurement confirms its capability to predict crosstalk in different MOSFET structures.

SiC double-trench MOSFETs with source-recessed structure for enhanced ruggedness

A novel SiC double-trench MOSFET (DT-MOS) with source-recessed structure is proposed and investigated via Sentaurus TCAD simulations in this paper. The lateral resistance area beneath the source region is completely eliminated, thus suppressing the turn-on of the parasitic npn transistor effectively. As a result, the short-circuit withstanding time, the single pulse avalanche energy (E av) under unclamped inductive switching test and the threshold voltage for single-event burnout are improved by 28%, 14% and 67%, respectively, when compared to the traditional state-of-the-art SiC DT-MOS, indicating its great potential for harsh environment applications.

4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics.

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

Analysis of the 1st and 3rd Quadrant Transients of Symmetrical and Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, performance at 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> and 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> quadrant operation of Silicon and Silicon Carbide (SiC) symmetrical and asymmetrical double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements using compact modeling. The devices are evaluated on a high voltage clamped inductive switching test rig and switched at a range of switching rates at elevated junction temperatures. It is shown, experimentally, that in the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> quadrant, CoolSiC (SiC asymmetrical double-trench) MOSFET and SiC symmetrical double-trench MOSFET demonstrate more stable temperature coefficients. Silicon Superjunction MOSFETs exhibits the lowest turn-off switching rates due to the large input capacitance. The evaluated SiC Planar MOSFET also performs sub-optimally at turn-on switching due to its higher input capacitance and shows more temperature sensitivity due to its lower threshold voltage. In the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> quadrant, the relatively larger reverse recovery charge of Silicon Superjunction MOSFET negatively impacts the turn-OFF transients compared with the SiC MOSFETs. It is also seen that among the SiC MOSFETs, the two double-trench MOSFET structures outperform the selected SiC planar MOSFET in terms of reverse recovery.

A Novel 1700V 4H-SiC Double Trench MOSFET Structure for Low Switching Loss

A Novel 1700V 4H-SiC Double Trench MOSFET Structure for Low Switching Loss

Numerical Simulation Analysis of Switching Characteristics in the Source-Trench MOSFET’s

In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ shielding region on the capacitance is analyzed, and the dynamic characteristics of the three structures are compared. The input capacitance is almost identical in all three structures. On the other hand, the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is reduced by 44% and 24%, respectively, compared to C-UMOSFET. Since the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is superior to that of C-UMOSFET, it improves high frequency figure of merit (HF-FOM: RON-SP × QGD). The HF-FOM of DT-MOSFET and ST-MOSFET is 289 mΩ∙nC, 224 mΩ∙nC, respectively, which is improved by 26% and 42% compared to C-UMOSFET. The switching speed of DT-MOSFET and ST-MOSFET are maintained at the same level as the C-UMOSFET. The switching energy loss and power loss of the DT-MOSFET and ST-MOSFET are slightly improved compared to C-UMOSFET.

Investigation on Surge Current Capability of 4H-SiC Trench-Gate MOSFETs in Third Quadrant Under Various V GS Biases

In this work, third-quadrant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> characterization and surge current tests are carried out on SiC asymmetric-trench MOSFET (DUT A) and SiC double-trench MOSFET (DUT B) under various gate–source biases ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> ). The surge capability is found to be uninfluenced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> for DUT A. However, it has a 71.4% increase when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> changes from 0 to −5 V for DUT B. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> characteristics in the third quadrant are measured under various <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> . It is found that the channel is open when the source–drain voltage is >2.5 V for DUT A and >1.5 V for DUT B at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V. High-temperature measurements are also conducted from 298 K to 448 K. When <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V, the channel current takes up to 50% at 10-A source-to-drain current for DUT B, whereas only 10% for DUT A. This could lead to high current/heat density in the channel of DUT B. The transient resistance is also extracted from the surge <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> trajectories, and it is higher for DUT B tested under <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V, which will increase the dissipated surge energy. Finally, the failure mechanism is analyzed. For DUT A, aluminum melting contributes to the failure at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}= -5$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V. For DUT B tested at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V, the earlier breakdown happens due to gate oxide failure.