Abstract
In this article, a novel silicon carbide double-trench MOSFET with an integrated fully depleted P-base MOS-channel diode is proposed and investigated by calibrated TCAD simulations. The proposed silicon carbide (SiC) MOSFET features a fully depleted P-base region achieved by shrinking the source trench mesa in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${z}$ </tex-math></inline-formula> -direction. Due to the significantly reduced conduction band energy in the fully depleted P-base region, a low potential barrier for electrons to flow through the JFET region to the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> source region is formed. As a result, the proposed SiC MOSFET not only exhibits more than three times lower diode cut-in voltage than the body p-i-n diode but also successfully eliminates the bipolar degradation issues. Besides, a compact model based on Poisson’s law is developed to understand the origin of the barrier lowering effect. Calibrated TCAD simulation results indicate that the enhanced third quadrant performance would not comprise the other electric characteristics, which makes the proposed SiC MOSFET a highly promising candidate for high-frequency power applications.
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