Double-trench MOSFET Research Articles

A trench/planar SiC MOSFET integrated with SBD (TPSBD) for low reverse recovery charge and low switching loss

In this paper, with Sentaurus TCAD simulation, the trench/planar MOSFET (TPMOS) shows a much lower electric field in gate oxide and a smaller gate charge than the traditional trench MOSFET (TMOS) and commercial double trench MOSFET (DTMOS). Besides, compared with DTMOS, the TPMOS also has a smaller specific on-resistance. These advantages make the TPMOS more suitable for being integrated with a Schottky barrier diode (SBD) to reduce both conduction loss and switching loss. Therefore, the trench/planar 4 H-SiC MOSFET integrated with SBD (TPSBD) is firstly proposed and studied. For the TPSBD, the static simulation results show that the maximum reverse current without the body diode turning on is 1320 A cm−2 in the third quadrant. In the double pulse test with a load current of 1000 A cm−2, the body diode of the TPSBD is successfully suppressed. However, the body diodes of the other three MOSFETs turn on and contribute 75% of the freewheeling currents, even though an external SBD is anti-parallel with these MOSFETs. The body diodes still contribute 25% of the freewheeling currents, even though the active area of the anti-parallel SBD increases three times. Compared with TMOS, DTMOS and TPMOS, the reverse recovery charge of the TPSBD reduces by 91%, 88% and 96%, respectively. The total switching loss of the TPSBD also reduces by 83%, 71% and 66% in contrast with TMOS, DTMOS and TPMOS, respectively. Therefore, the TPSBD is a superior choice for low reverse recovery charge and low switching loss application.

A heterojunction-based SiC power double trench MOSFET with improved switching performance and reverse recovery

Abstract In this paper, a heterojunction-based SiC double trench MOSFET (HJ-DTMOS) is proposed to improve its switching performance and the reverse recovery characteristic. In the HJ-DTMOS, a n+p− polysilicon junction is introduced in both the gate trench and the source trench. For the source trench, the heterojunction formed by the p− polysilicon layer and drift silicon carbide layer functions as a body diode in parallel with the device which shows a significant reduction in term of the reverse recovery charge and the on-state voltage. The n+p− junction in the gate trench introduces an additional depletion capacitance between the gate electrode and the drain electrode, which efficiently reduces the total Cgd, thus reducing the switching loss of the HJ-DTMOS. Simulation results show that the proposed new device is preferred in high-frequency and high-efficiency power applications.

SiC Double-Trench MOSFETs With Embedded MOS-Channel Diode

A novel SiC double-trench MOSFET (DT-MOS) with embedded MOS-channel diode is proposed and investigated via TCAD simulations in this article. The parasitic body diode is free from activation when the device serves as a freewheeling diode, thus completely eliminating the bipolar degradation. Moreover, the proposed MOSFET features superior dynamic characteristics. The gate charge ( ${Q}_{\text {G}}$ ) and gate-to-drain charge ( ${Q}_{\text {GD}}$ ) are reduced by a factor of ~1.8 and ~3.9, respectively, when compared to the conventional state-of-the-art SiC DT-MOS. Combined with the slightly increased ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ), remarkably improved figures of merit ( ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {G}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}\times {Q}_{\text {GD}}$ are reduced by a factor of ~1.7 and ~3.7, respectively) are obtained in the proposed structure. When working as a switching device under 200 kHz, the proposed MOSFET could save nearly 64% of the total power losses, making it more conductive to high-frequency applications. In addition, the influence of parameters variation on the device performance is discussed as well.

Single-Event Effects in SiC Double-Trench MOSFETs

Single-event effects (SEEs) in a 650-V state-of-the-art SiC double-trench MOSFET (DT-MOS) are investigated using the Sentaurus TCAD tools. The safe operation areas (SOAs) for single-event burnout (SEB) and single-event gate rupture (SEGR) are extracted when heavy ions with different linear energy transfer (LET) impact the sensitive regions of the device. The results show that the radiation performance of the SiC DT-MOS is poor because of the very low threshold voltages of failures at a high LET range. Moreover, hardening measures, such as introducing a buffer layer and adjusting the mesa width, are discussed to assess their versatility. It is demonstrated that in contrast, the SEGR problem is more severe due to the intrinsic properties of SiC devices. Therefore, it becomes a crucial issue to find ways more suitable for the SiC DT-MOS to avoid gate oxide pre-breakdown, before they could serve as a replacement of Si counterparts in space applications.

Study of Asymmetric Cell Structure Tilt Implanted 4H-SiC Trench MOSFET

The reliability of gate dielectrics is one of the key issues in SiC Trench MOSFET. While reducing the gate oxide electric field in OFF state through dedicated shielding structures by various designs, JFET resistances are often introduced. In this letter, a new asymmetric cell structure, tilt implanted 4H-SiC trench MOSFET (ACTI-TMOS) is proposed. This approach achieves a better trade-off between gate oxide electric field and specific ON-resistance ( $R_{ \mathrm{\scriptscriptstyle ON}}$ ). The 2D numerical simulation was used to compare ACTI-TMOS with double trench MOSFET and gate bottom p-well trench MOSFET. The maximum gate oxide electric field of the ACTI-TMOS is 42.1% and 6.5% lower in OFF state compared to the other two designs. Both gate charge ( $Q_{G}$ ) and gate drain charge ( $Q_{GD}$ ) are significantly improved. The results show that ACTI-TMOS is a more attractive device structure.

A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

A new ultralow gate–drain charge (QGD) 4H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures (DS-MOS): one is the grounded split gate (SG), the other is the P+ shielding region (PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance (CGD) into the gate–source capacitance (CGS) and drain–source capacitance (CDS) in series. Thus the CGD is reduced and the proposed DS-MOS obtains ultralow QGD. Compared with the double-trench MOSFET (DT-MOS) and the conventional trench MOSFET (CT-MOS), the proposed DS-MOS decreases the QGD by 85% and 81%, respectively. Moreover, the figure of merit (FOM), defined as the product of specific on-resistance (Ron, sp) and QGD (Ron, spQGD), is reduced by 84% and 81%, respectively.

Role of Trench Bottom Shielding Region on Switching Characteristics of 4H-SiC Double-Trench Mosfets

The effect of a gate trench bottom p+ region (BPR) on the dynamic characteristics of 4H-SiC double-trench MOSFETs was investigated. Although employing a BPR led to an improved trade-off in the static characteristics, a BPR adversely affected the switching characteristics in spite of a reduction in the Miller capacitance compared to the case without a BPR. Simulation analysis revealed that a resistance between a BPR and a source electrode led to an increase in the switching loss. We have found reduction of the resistance is insufficient in order to provide benefits from the BPR. Hence, it is necessary to improve layouts of contacts of the BPR to the source electrode.

4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-controlled Gate Structure

A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-controlled gate structure (FJB-MOS/GJB-MOS) is presented and investigated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance ( ${V}_{\textsf {BR}}^{{\,\textsf {2}}}/{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific gate–drain charge ${Q}_{{\:\textsf {gd,sp}}}$ and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.

SiC Trench MOSFET With Shielded Fin-Shaped Gate to Reduce Oxide Field and Switching Loss

A silicon carbide shielded fin-shaped gate metal-oxide-semiconductor field effect transistor (SF-MOS) is proposed in this letter, which utilizes a well-grounded p-region to shield the fin-shaped trench gate. Numerical simulations by Sentaurus TCAD are carried out to study the performance of SF-MOS, and comparisons with conventional trench MOSFET and the state-of-the-art double-trench MOSFET are presented. The maximum electric field in gate oxide of the SF-MOS is effectively lowered to below 3 MV/cm, which is a widely accepted criterion for long-term gate oxide reliability. Furthermore, with the shielding effects, the gate-to-drain charge of the SF-MOS is significantly reduced, leading to lower switching loss.

SiC Trench Devices with Ultra Low Ron

SiC devices have the potential to reduce energy losses in high power applications. However SiC devices have yet to achieve ideal performance levels. This paper presents SiC diodes and MOSFETs with advanced trench structures. These devices succeeded in improving performance by reduction of the internal electric field. Trench Schottky diodes are able to reduce forward voltage drop and double-trench MOSFETs show extremely low on-resistance.

690V, 1.00 mΩcm<sup>2</sup> 4H-SiC Double-Trench MOSFETs

The trench gate structure MOSFET, with its lack of JFET resistance, is one of the structures able to achieve low on-state resistance [1,2]. In 2008, this group succeeded in fabricating 790V SiC trench MOSFETs with the lowest Ron,sp (1.7 mΩcm2) at room temperature. However these devices had issues regarding oxide destruction at the trench bottom during high drain-source voltage application. In order to improve this problem, this group developed the double-trench MOSFET structure. This structure has both source trenches and gate trenches. This paper compares two kinds of trench MOSFETs: the conventional, single trench structure and a double-trench structure. Also, the latest characteristics are presented.