Double-sided Silicon Strip Sensors Research Articles

Double-sided silicon strip sensors formed by concatenated drift cells

Double-sided Silicon Strip sensors (DSSD) can cover large areas and volumes of silicon with a relatively small amount of readout channels. If used for spectroscopy though, their resolution is limited by the large readout capacitance of p- and n-side strips. This paper presents the idea of small Silicon Drift Detector (SDD) cells whose anodes are connected to form n-side strips similar to double-sided strip sensors. Their combined n-side capacitance should be significantly lower than continuous strips and improve spectroscopic energy resolution. The p-side strips are used to deliver a prompt trigger signal and position information. Such concatenated sdds (c-SDD) can only be reasonably implemented for a strip pitch larger than the wafer thickness.

A 64 channels ASIC for the readout of the silicon strip detectors of the PANDA micro-vertex detector

The ToASt ASIC is a 64 channel integrated circuit designed for the readout of the double-sided silicon strip sensors that will equip the micro-vertex detector of the PANDA experiment. The ToASt ASIC operates with a 160 MHz clock, which defines also the time resolution. A common time stamp is distributed to all channels to provide a common time reference for time of arrival and time over threshold measurements. Two 160 Mb/s serial lines provide the interface to the data concentrator. ToASt is implemented in a commercial 110 nm CMOS technology with triplicated logic to protect against single event upsets.

Performance and running experience of the Belle II silicon vertex detector

The Belle II silicon vertex detector is one of the vertex detectors in the Belle II experiment. The detector reads out the signals from the double-sided silicon strip sensors with the APV25 front-end readout ASIC, adopting the chip-on-sensor concept to minimize the strip noise. The detector has been operated in the experiment since the spring of 2019. Analyzing the acquired data during the beam collisions, the excellent performance of the detector is confirmed. Also, the radiation dose and 1-MeV equivalent neutron fluence of the detector are estimated using the measured dose rates of the diamond sensors installed on the beam pipe and are compared with the measured radiation effects in the strip noise, leakage current, and depletion voltage. This paper briefly introduces the main features of the silicon vertex detector, and then reports on the measured performance and radiation effects of the first two years of running experience of the detector.

The design, construction, operation and performance of the Belle II silicon vertex detector

The Silicon Vertex Detector of Belle II is a state-of-the-art tracking and vertexing system based on double-sided silicon strip sensors, designed and fabricated by a large international collaboration in the period 2012–2018. Since 2019 it has been in operation providing high quality data with a small number of defective channels (<1%), a large hit-finding efficiency (>99%), a good signal-to-noise ratio (well in excess of 10 for all sensor configurations and tracks). Together with the good control over the alignment, these are all essential factors to achieve good tracking reconstruction and physics performance. In this extended paper we try to document all the aspects of the SVD challenges and achievements, in the spirit of providing information to the broader community and help the development of high quality detector systems, which are essential tools to carry out physics research.

The silicon vertex detector of the Belle II experiment

In 2019 the Belle II experiment started data taking at the asymmetric SuperKEKB collider (KEK, Japan) operating at the Y(4S) resonance. Belle II will search for new physics beyond the standard model by collecting an integrated luminosity of 50 ab−1. The silicon vertex detector (SVD), consisting of four layers of double-sided silicon strip sensors, is one of the two vertex sub-detectors. The SVD extrapolates the tracks to the inner pixel detector (PXD) with enough precision to correctly identify hits in the PXD belonging to the track. In addition the SVD has standalone tracking capability and utilizes ionization to enhance particle identification in the low momentum region. The SVD is operating reliably and with high efficiency, despite exposure to the harsh beam background of the highest peak-luminosity collider ever built. High signal-to-noise ratio and hit efficiency have been measured, as well as the spatial resolution; all these quantities show excellent stability over time. Data-simulation agreement on cluster properties has recently been improved through a careful tuning of the simulation. The precise hit-time resolution can be exploited to reject out-of-time hits induced by beam background, which will make the SVD more robust against higher levels of background. During the first three years of running, radiation damage effects on strip noise, sensor currents and depletion voltage have been observed, as well as some coupling capacitor failure due to intense radiation bursts. None of these effects cause significant degradation in the detector performance.

Measurement of the cluster position resolution of the Belle II Silicon Vertex Detector

The Silicon Vertex Detector (SVD), with its four double-sided silicon strip sensor layers, is one of the two vertex sub-detectors of Belle II operating at SuperKEKB collider (KEK, Japan). Since 2019 and the start of the data taking, the SVD has demonstrated a reliable and highly efficient operation, even running in an environment with harsh beam backgrounds that are induced by the world’s highest instantaneous luminosity.In order to provide the best quality track reconstruction with an efficient pattern recognition and track fit, and to correctly propagate the uncertainty on the hit’s position to the track parameters, it is crucial to precisely estimate the resolution of the cluster position measurement. Several methods for estimating the position resolution directly from the data will be discussed.

Commissioning of the Belle II Silicon Vertex Detector

The Belle II experiment at the SuperKEKB collider of KEK (Japan) will accumulate 50 ab−1 of e+e- collision data at an unprecedented instantaneous luminosity of 8⋅ 1035 cm−2s−1, about 40 times larger than its predecessor. The Belle II vertex detector plays a crucial role in the rich Belle II physics program, especially for time-dependent measurements. It consists of two layers of DEPFET-based pixels and four layers of double sided silicon strip sensors (SVD detector). We report here results of the standalone commissioning of the SVD and highlights from the first cosmic runs acquired in Belle II. We also report on reconstruction performances of a reduced-scale version of the SVD operated during the accelerator commissioning in 2018.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

Detector production for the R3B Si-tracker

R3B is a fixed target experiment which will study reactions with relativistic radioactive beams at FAIR. Its Si-tracker will surround the target volume and it will detect light charged-particles like protons.The detector technology in use consists of double-sided silicon strip sensors wire bonded to the custom made R3B-ASIC.The tracker allows for a maximum of two outer layers and one inner layer. This paper reports on the production of detectors necessary to build the minimum tracking configuration: one inner layer and one outer layer.

CERBEROS: A tracking system for secondary pion beams at the HADES spectrometer

In 2014 the HADES collaboration performed two successful physics production runs with secondary pion beams. Since secondary pion beams are strongly defocussed in position and momentum, two fast tracking stations were installed along the pion beam chicane following the pion production target providing the momentum measurement of each individual pion. The momentum is reconstructed using the position information of every hit detected by the tracking stations and the beam optics transport calculation with a resolution below 0.5% playing an important role in terms of the exclusive analysis of investigated reactions.Both tracking stations consist of a double-sided silicon strip sensor with a large active area (10×10cm2). To guarantee fast tracking, the sensors are read out with the n-XYTER ASIC chip. Due to its self-triggering architecture and local storage capability, the chip enables on-line tracking at high rates (dN/dt>106part/s). The TRB3 read out board on which the trigger logic is implemented integrates the system into the HADES DAQ.In this report we are showing the results obtained during the calibration experiment with a monochromatic proton beam set at seven different momenta centred around 2.68GeV/c. Also the excellent performance achieved during the production campaign with a pion beam are presented.

The readout chain for the P̄ANDA MVD strip detector

The P̄ANDA (antiProton ANnihilation at DArmstadt) experiment will study the strong interaction in annihilation reactions between an antiproton beam and a stationary gas jet target. The detector will comprise different sub-detectors for tracking, particle identification and calorimetry. The Micro-Vertex Detector (MVD) as the innermost part of the tracking system will allow precise tracking and detection of secondary vertices. For the readout of the double-sided silicon strip sensors a custom-made ASIC is being developed, employing the Time-over-Threshold (ToT) technique for digitization and utilize time-to-digital converters (TDC) to provide a high-precision time stamp of the hit. A custom-made Module Data Concentrator ASIC (MDC) will multiplex the data of all front-ends of one sensor towards the CERN-developed GBT chip set (GigaBit Transceiver). The MicroTCA-based MVD Multiplexer Board (MMB) at the off-detector site will receive and concentrate the data from the GBT links and transfer it to FPGA-based compute nodes for global event building.

A Low Mass On-Chip Readout Scheme for Double-Sided Silicon Strip Detectors

B-factories like the KEKB in Tsukuba, Japan, operate at relatively low energies and thus require detectors with very low material budget in order to minimize multiple scattering. On the other hand, front-end chips with short shaping time like the APV25 have to be placed as close to the sensor strips as possible to reduce the capacitive load, which mainly determines the noise figure.In order to achieve both – minimal material budget and low noise – we developed a readout scheme for double-sided silicon detectors, where the APV25 chips are placed on a flexible circuit, which is glued onto the top side of the sensor. The bottom-side strips are connected by two flexible circuits, which are bent around the edge of the sensor.This so-called “Origami” design will be utilized to build the Silicon Vertex Detector of the Belle II experiment, which will consist of four layers made from ladders with up to five double-sided silicon strip sensors in a row. Each ladder will be supported by two ribs made of a carbon fiber and Airex foam core sandwich. The heat dissipated by the front-end chips will be removed by a highly efficient two-phase CO2 system. Thanks to the Origami concept, all APV25 chips are aligned in a row and thus can be cooled by a single thin cooling pipe per ladder.We present the concept and the assembly procedure of the Origami chip-on-sensor modules.

The Belle II Silicon Vertex Detector

The KEKB machine and the Belle experiment in Tsukuba (Japan) are now undergoing an upgrade, leading to an ultimate luminosity of 8×1035cm−2s−1 in order to measure rare decays in the B system with high statistics.The previous vertex detector cannot cope with this 40-fold increase of luminosity and thus needs to be replaced. Belle II will be equipped with a two-layer Pixel Detector surrounding the beam pipe, and four layers of double-sided silicon strip sensors at higher radii than the old detector. The Silicon Vertex Detector (SVD) will have a total sensitive area of 1.13m2 and 223,744 channels—twice as many as its predecessor.All silicon sensors will be made from 150mm wafers in order to maximize their size and thus to reduce the relative contribution of the support structure. The forward part has slanted sensors of trapezoidal shape to improve the measurement precision and to minimize the amount of material as seen by particles from the vertex. Fast-shaping front-end amplifiers will be used in conjunction with an online hit time reconstruction algorithm in order to reduce the occupancy to the level of a few percent at most. A novel “Origami” chip-on-sensor scheme is used to minimize both the distance between strips and amplifier (thus reducing the electronic noise) as well as the overall material budget.This report gives an overview on the status of the Belle II SVD and its components, including sensors, front-end detector ladders, mechanics, cooling and the readout electronics.

The front-end chip of the SuperB SVT detector

The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.

Recent progress in sensor- and mechanics-R&D for the Belle II Silicon Vertex Detector

The Belle experiment at the KEKB electron/positron collider in Tsukuba (Japan) was successfully running for more than ten years. A major update of the machine to SuperKEKB is now foreseen until 2015, aiming a peak luminosity which is 40 times the peak value of the previous system. This also requires a redesign of the Belle detector (leading to Belle II) and especially its Silicon Vertex Detector (SVD), which surrounds the beam pipe.The future Belle II SVD will consist of four layers of double-sided silicon strip sensors based on 6in. silicon wafers. Three of the four layers will be equipped with trapezoidal sensors in the slanted forward region. Moreover, two inner layers with pixel detectors based on DEPFET technology will complement the SVD as innermost detector. Since the KEKB-factory operates at relatively low energy, material inside the active volume has to be minimized in order to reduce multiple scattering. This can be achieved by arranging the sensors in the so-called “Origami chip-on-sensor concept”, and a very light-weight mechanical support structure made from carbon fiber reinforced Airex foam. Moreover, CO2 cooling for the front-end chips will ensure high efficiency at minimum material budget.In this paper, an overview of the future Belle II SVD design will be given, covering the silicon sensors, the readout electronics and the mechanics. A strong emphasis will be given to our R&D work on double-sided sensors where different p-stop layouts for the n-side of the detectors were compared. Moreover, this paper gives updated numbers for the mechanical dimensions of the ladders and their radii.

The Belle II Silicon Vertex Detector

Abstract The KEKB factory (Tsukuba, Japan) has been shut down in mid-2010 after reaching a total integrated luminosity of 1ab -1 . Recently, the work on an upgrade of the collider (SuperKEKB), aiming at an ultimate luminosity of 8×10 35 cm -2 s -1 , has started. This is 40 times the peak value of the previous system and thus also requires a redesign of the Belle detector (leading to Belle II), especially its Silicon Vertex Detector (SVD), which surrounds the beam pipe. Similar to its predecessor, the future Belle II SVD will again consist of four layers of double-sided silicon strip sensors (DSSD), but at higher radii. Moreover, a double-layer PiXel Detector (PXD) will complement the SVD as the innermost sensing device. All DSSDs will be made from 6” silicon wafers and read out by APV25 chips, which were originally developed for the CMS experiment. That system was proven to meet the requirements for Belle II in matters of occupancy and dead time. Since the KEKB factory operates at relatively low energy, material inside the active volume has to be minimized in order to reduce multiple scattering. This can be achieved by the Origami chip-on-sensor concept, including a very light-weight mechanical support structure made from carbon fiber reinforced Airex foam. Moreover, CO2 cooling for the front-end chips will ensure high efficiency at minimum material budget.

FPGA-based readout for double-sided silicon strip detectors

This work presents an FPGA-based readout system for double-sided silicon strip sensors based on the APV25 front-end chip. The system consists of an ADC-card and a digital readout board containing an FPGA. Data extraction algorithms implemented in the FPGA allow baseline and pedestal correction, hit detection and event-building. These algorithms represent an efficient data reduction tool and provide high readout rates.Details of the system, the algorithms applied and performance will be discussed featuring data collected in various tests experiments.

Fabrication of AC-coupled double-sided silicon strip sensor

The AC-coupled double-sided silicon microstrip sensors are designed and 14 masks are used to produce prototype strip sensors. The biasing resistors are made of p-doped polysilicons and the coupling capacitors are built by separating implanted strips and readout strips by a thin oxide layer. The p-stops in the atoll patterns are introduced to disrupt an electron accumulation layer at the Si–SiO2 interface on the ohmic side. The junction side has a double metal structure using two metal layers separated from each other by a thick insulator layer. The strip sensors are fabricated on a 5-in., high resistivity, 〈100〉-orientation, and 380μm thick n-type double-sided polished silicon wafer. The prototype sensor with an area of 2.8×2.8cm2 consists of 256(512) readout channels with a strip pitch of 100(50)μm. The leakage currents and the bulk capacitances as a function of the reverse bias voltage are measured to understand the fabrication process of the prototype sensors. The signal to noise ratios are measured by using a 90Sr radioactive source in order to evaluate performance of the sensors. The design of the AC-coupled double-sided silicon strip sensor and its various components are described, and measurements of the electric characteristics and the signal to noise ratio are presented.

Performance Tests of a Silicon Strip Detector with Radioactive Sources and Proton Beam

We fabricated an AC-coupled single-sided silicon strip sensor and an DC-coupled double-sided silicon strip sensor on a 5-in. 380-μm-thick wafer. The single-sided strip sensor has a size of 3.2 cm × 3.2 cm and 64 implanted and readout strips with a strip pitch of 500 μm. On the other hand, the double-sided strip sensor has an active size of 5.6 cm × 3.0 cm and 512 readout strips with a strip pitch of 50 μm. Two low-noise analog ASIC VA1 and VA1TA chips were used for signal readout of the single-sided strip and the double-sided strip sensors, respectively. The data acquisition system was based on a 12-bit 64-MHz Flash analog-to-digital converter (FADC) and control software for the PC-Linux platform. The signal-to-noise ratios of the sensor were measured with radioactive sources and a 45-MeV proton beam of the MC-50 cyclotron at Korea Institute of Radiological and Medical Sciences (KIRAMS). The performance results of the manufactured AC-coupled single-sided silicon strip detector and DC-coupled double-sided silicon strip detector are presented.

Fabrication and Beta-Ray Source Test of Double-Sided Silicon Strip Sensor

Since a double-sided silicon strip sensor provides two-dimensional position information with high resolution, it has been developed for various uses as a medical imaging sensor, radiation detector, sensing detector in space science, and a silicon vertexing/tracking detector in experimental particle physics. We designed and fabricated a double-sided silicon position sensor in a 5 in. fabrication line. Silicon nitride with a silicon oxide layer was used to prevent damage during sensor fabrication. Since the temperature dependences of the silicon nitride and the silicon oxide are different, the thicknesses of the Si3N4 and SiO2 layers were optimized using the ATHENA process simulation to avoid cracks. We present the measurement results of the electrical characteristics of the sensor such as leakage current and capacitance as a function of reverse bias voltage. We performed tests on the sensor using a 90Sr radioactive source and measured the signal-to-noise ratio of the prototype sensor.