Double Pulse Test Research Articles

A Temperature-Dependent dVCE/dt Model for Field-Stop IGBT at Turn-Off Transient

In this paper, an analytical model is proposed to model collector-emitter voltage rising slope ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV_CE/dt</i> ) of field-stop (FS) IGBT during turn-off transient. Thanks to TCAD simulation, the internal physics of the FS IGBT during <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_CE</i> rise transient is investigated. Based on the improved understanding of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_CE</i> rise transient, an analytical solution of the excess carrier distribution in the N-base region and FS layer is derived. An analytical model for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV_CE/dt</i> of FS IGBT is also proposed. The temperature dependency of various silicon material and device parameters are included in the model. In the end, the double-pulse tests are performed on 650V/40A and 1200V/40A FS IGBTs. The test results are compared with the analytical predictions and good agreement is obtained.

Double Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification

Wide Bandgap devices (WBG) have led to an era of high speed and high voltage operations that were not previously achievable with silicon devices. However, packaging of these devices in the power module has been a challenge due to higher switching rates which can cause several amperes of displacement current to flow through the parasitic capacitance of the package thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates unlike the traditional inorganic substrates e.g. DBC and thus a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this paper is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and RMS value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.

Active Gate Driver for Dynamic Current Balancing of Parallel-Connected SiC MOSFETs

In high-power applications, parallel connection of discrete silicon carbide (SiC) MOSFETs is necessary to increase the current rating. However, the unbalanced dynamic current during switching transient may cause unequal power loss and thermal distribution, which is a great challenge in parallel applications. In this paper, a dynamic current balancing method based on a new active gate driver (AGD) is proposed to improve the current sharing. The principle of the AGD is based on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> feedback control and voltage controlled current source to adjust gate drive current of SiC MOSFETs. Therefore, the switching trajectory of the paralleled devices can be changed to achieve current balance. In addition, by using master-slave control strategy, the proposed AGD can be easily used for multiple paralleled devices. The double pulse tests are conducted to verify the effectiveness of the proposed AGD. For two paralleled devices, the turn-on and turn-off switching energy imbalances are reduced from 13.4% and 56.0% (12.1% and 52.9%) to 8.8% and 15.3% (8.0% and 8.8%) by the current source (current sink) circuit. For six paralleled devices, the degrees of turn-on and turn-off switching energy imbalances can be reduced from 21.8% and 16.1% to 11.8% and 7.8% by the proposed AGD. <fn fn-type="other" id="fn3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This work was supported by Key-Area Research and Development Program of Guangdong Province under Grant 2021B0101310004, and the research program sponsored by Eaton. (<i>Corresponding author</i>: <i>Junming Zhang</i>) Y. He, X. Wang, S. Shao, and J. Zhang are with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: ; ; ; ). </fn>

A Miniaturized Sealed-Off Double-Gap Pseudospark Switch for High Power and High Repetition Rate Pulsed Discharge Applications

Pulsed power systems can deliver high peak power in a micro/nano-second timescale to various loads in scientific and industrial applications, whose performances are significantly influenced by the pulsed discharge switch. This paper presents the development and comprehensive tests of a miniaturized sealed-off pseudospark switch. The structure of double-gap and multi-channel is adopted to achieve the high hold-off voltage and high current capacity. In single pulse tests, the influence of pressure in the switch is analyzed. As the pressure increases, values of multiple parameters decrease, like self-breakdown voltage, trigger delay, and voltage dropping time. In a wide pressure range, trigger jitter is below 3 ns, and the minimum is < 1 ns. At low pressure, the transient voltage across two gaps becomes inconsistent, and two types of current quenching are observed, which are related to processes occurring on cathode surface. In repetitive pulse tests, the direct repetitive operation is up to 3.5 kHz while higher repetition rate is limited by the trigger system. In double-pulse tests, the maximum repetition rate can be higher than 8 kHz for 40 kV pulsed voltage. Meanwhile, the insulation recovery speed is higher at lower pressure, and as the time delay between two pulses increases, the second pulse breakdown voltage increases nonlinearly. In high current tests, the switch is also used in metal wire explosion experiments and operates at the condition of 30 kV/40 kA for more than 104 shots without performance degradation. Further lifetime tests point out that the switch can work for >106 shots stably at moderate current. Experiments prove that the designed switch has superior performances including high hold-off voltage (>50 kV), low jitter (<1 ns), high repetition rate (>3.5 kHz), high peak current (>40 kA), long lifetime (>106 shots) and miniaturized size.

High Bandwidth Active Gate Driver for Simultaneous Reduction of Switching Surge and Switching Loss of SiC-MOSFET

This study investigates an active gate driver (AGD) for an SiC-MOSFET. The source current feedback type AGD utilizes the induced voltage of the source wire inductance as a negative feedback signal to regulate the source current di/dt. Recent improvements in the switching performance of the AGD is limited due to the feedback system bandwidth. In this paper, a high bandwidth current feedback type power operational amplifier is applied as the gate drive circuit. Switching characteristics of the conventional resistive gate driver and AGD are experimentally investigated via a double pulse test setup. The switching setup condition is 700 V / 80 A. This paper describes the development of the AGD circuit and experimental results. The over-shoot and ringing of the Vds and Is are reduced using the AGD. Moreover, the switching loss is simultaneously reduced.

Double-Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification

Wide Bandgap devices (WBG) have led to an era of high-speed and high-voltage operations that were not previously achievable with silicon devices. However, packaging these devices in the power module has been a challenge due to higher switching rates, which can cause several amperes of displacement current to flow through the parasitic capacitance of the package, thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates, unlike the traditional inorganic substrates, e.g., Direct Bond Copper (DBC) and thus, a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this article is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and Root Mean Square (RMS ) value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.

An Electric Field Probe With High Immunity for SiC MOSFET Switching Voltage Measurement

Accurate measurement of switching voltage is the basis for evaluating the dynamic behavior of power devices. With the development of wide bandgap (WBG) devices, the high switching speed of the silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs) imposes high bandwidth and strong immunity requirements on the voltage probe. The electric field probe (EFP) based on the principle of electric field coupling has a naturally high bandwidth, which can be considered as a potential competitor. However, due to the noncontact suspended measurement method, the interference signal is easily coupled by the EFP and affects the measurement accuracy. Thus, this article proposes a high noise-immune structure for EFP to implement the measurement of SiC MOSFET switching voltage. The EFP is manufactured from the printed circuit board (PCB), which can provide a more accurate parameter design. Then, the shielded copper clad and via arrays structures are proposed, and the effectiveness of the shielding structure is verified by adding an interference source. Finally, through the double-pulse test, it is demonstrated that the performance of the proposed EFP is sufficient to measure the switching voltage of SiC MOSFETs.

Design and Implementation of a Paralleled Discrete SiC MOSFET Half-Bridge Circuit with an Improved Symmetric Layout and Unique Laminated Busbar

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB®/Simulink® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented.

Design and Evaluation of a Face-Down Embedded SiC Power Module With Low Parasitic Inductance and Low Thermal Resistance

This letter proposed an embedded silicon carbide (SiC) power module with low parasitic inductance and low thermal resistance for high-frequency and high-temperature applications. The SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s were oriented in a face-down configuration with Cu connecting blocks, contributing to better switching performance and heat dissipation. The simulation results showed that the total parasitic inductance was lower than 300 pH. Double pulse test and thermal resistance experiments compared with a commercial package showed that the switching loss and the junction-to-case resistance of the proposed module were reduced by 23% and 35%, respectively.

An Accurate Analytical Model of SiC MOSFETs for Switching Speed and Switching Loss Calculation in High-Voltage Pulsed Power Supplies

Nanosecond output pulse and high efficiency are achieved in high-voltage pulsed power supplies (HVPPSs) by applying silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s), whose switching speed and switching loss are two vital characteristic parameters. However, the existing research on switching characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is mainly based on the double pulse test circuits with inductive loads, which is not suitable for assessing the devices in HVPPSs with resistive loads. Besides, some simplified analytical methods in HVPPSs lead to poor precision. To accurately predict the switching behavior of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in HVPPSs for guiding the design of gate driving circuits and power loops, this article proposes an accurate analytical model considering parasitic inductances, nonlinear parasitic capacitances, transfer characteristic, and output characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. High-precision fitting of transfer characteristic is realized by using the Gaussian function. Besides, the dynamic parasitic gate-drain capacitance is measured by experiment, and three-dimensional curve fitting is performed on the output characteristics to exactly represent <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance. Furthermore, switching speed and switching loss can be directly calculated according to the solved state variables. Finally, the analytical model is verified by experiment, and the effects of gate driving circuits and power loops on switching characteristics are researched in detail.

Gate Drive Circuit Implementation for Parallel Connection of Power Devices Considering Parasitic Inductance

SiC devices are potential future power devices because of their higher switching speed and lower ON resistance than those of Si devices. Research and development efforts to apply them in medium- and large-capacity power conversion circuits are underway. However, SiC power devices in TO packages, which are general-purpose packages, are difficult to apply in high-current applications owing to their low current ratings. Therefore, increasing the capacity of power devices by connecting them in parallel is being studied. However, the current imbalance during switching due to the differences in device characteristics and variations in parasitic inductance is problem. This study proposed a current-balancing procedure focused on the parasitic inductances around power devices and gate drive circuit implementation. The proposed method was verified by conducting double-pulse tests at 300V and 200A.

Improved Double Pulse Test for Accurate Dynamic Characterization of Medium Voltage SiC Devices

This article presents an improved double pulse test (DPT) for accurate dynamic characterization of the medium voltage (MV) silicon carbide device. The difference between low voltage (LV) and MV DPT setup grounding is first introduced, which results in different measurement considerations. Then, parasitic capacitances in the DPT and their impact on the DPT are discussed considering different grounding points and device connections. Approaches are proposed to minimize the impact of parasitic capacitances on DPT results. In addition, the impact of switching V-I timing alignment on the testing results is discussed, compared to that in the LV DPT; a V-I alignment approach is introduced for the MV DPT. A 10 kV/20 A SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> -based DPT is taken as an example of the improved DPT, and test results show that it can minimize the impact from parasitic and improve the accuracy of the device switching loss estimation.

H-Bridge Derived Topology for Dynamic On-Resistance Evaluation in Power GaN HEMTs

Gallium nitride high electron mobility transistors outperform Silicon devices due to their excellent physical properties. However, being an immature technology, it exhibits dynamic <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$R_{\text{ds}, \text{on}}$</tex-math></inline-formula> ). This causes increased conduction loss and leads to reduced operating efficiency. To evaluate the dynamic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$R_{\text{ds}, \text{on}}$</tex-math></inline-formula> of the device, a measurement circuit is required. In literature, a standardized double pulse test is widely used for the measurement of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$R_{\text{ds}, \text{on}}$</tex-math></inline-formula> . However, due to the uncontrolled <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> -state time and inability to independently adjust, the test conditions result in restricted measurement. This article proposes a measurement circuit of the device in power electronics operations. The circuit uses an H-Bridge-derived topology with capacitive storage to enable forward and reverse conduction mode measurement of the device. In all the modes, the circuit allows measurement from the first switching cycle and independent control over the testing conditions by using a hysteresis current control. The proposed measurement circuit is validated using simulation and experimentation. Finally, analytical efficiency compared with the state-of-the-art measurement circuits is provided.

Analysis of Dead-Time Energy Loss in GaN-Based TCM Converters With an Improved GaN HEMT Model

For gallium nitride (GaN) based triangular current mode (TCM) applications, the dead-time has a significant effect on the switching loss. However, previous GaN high electron mobility transistor (HEMT) models focus on the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on/off</small> process without fully considering the effect of the dead-time. Hence, this article analyzes the switching transients under the superfluous and insufficient dead-time and evaluates the dead-time loss with an improved GaN HEMT model. The proposed model improves an existing GaN HEMT model by adding the voltage rising/falling time of the gate driver, the dynamic threshold voltage of Schottky-type GaN HEMTs, and an equivalent gate-drain capacitance obtained from the datasheet. Verified by a GaN-based double-pulse test, the proposed model can more accurately calculate the gate-source voltage and the self-commutated reverse conduction voltage. Verified by a GaN-based TCM Buck converter, the proposed model can predict the dead-time loss well and has higher simulation accuracy for the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> process induced by the inappropriate dead-time.

The impact of DC-bus impedance on the switching performance of low-voltage silicon power MOSFETs

Typical DC-bus stabilization for low-voltage power circuits consists primarily of ceramic capacitors due to the capacity density and low equivalent series resistance (ESR) resulting in low conduction losses. Particularly in hard-switching and hard-commutation operation, the low ESR and high equivalent series inductance (ESL) of the capacitors in the commutation path restrict the damping of the switch node voltage overshoot and introduce high-frequency ringing, reducing the voltage margin of the transistor. Therefore, this paper analyzes the impact of the DC-bus impedance and proposes a DC-bus snubber based on an RC network to form the DC-bus impedance’s characteristic, which minimizes the overshoot voltage. A comprehensive simulation using measurement-derived component models is shown, which is verified by an in-situ measurement on a test PCB. Furthermore, transient measurements using a double pulse test setup show the effectiveness of the proposed approach.

Influence of driving and parasitic parameters on the switching behaviors of the SiC MOSFET

The SiC MOSFET has lower conduction loss and switching loss than the Si IGBT, which helps to improve the efficiency and power density of the converter, especially for those having strict requirements for volume and weight, for example, electrical vehicles (EVs), on-board chargers (OBCs), and traction drive systems (TDS). However, the faster switching speed will cause overshoot and oscillation problems, which will affect the efficiency and security of the SiC devices and power electronic systems. For the SiC MOSFET to be better used, combining a theoretical analysis, the double-pulse test platform is built. The controllable principles of SiC MOSFETs are validated. The turn-on and turn-off delay, switching delay, switching di/dt, switching du/dt, switching overshoot, and switching loss of SiC MOSFETs under different driving and parasitic parameters are explored. Finally, some valuable suggestions for designing are proposed for a better application of the SiC MOSFET.

A High-Bandwidth and Easy-to-Integrate Parasitics-Based Switching Current Measurement Method for Fast GaN Devices

While the very high switching speed of the gallium nitride devices can easily enable power electronics converters to operate at multi megahertz, it also brings huge challenges to switching current measurement, which is very important for the evaluation of switching performance. The conventional switching current measurement methods either have low bandwidth or have influence on layout inductance. To address these issues, this article proposes a high-bandwidth and easy-to-integrate switching current measurement method, with almost no influence on power loop layout. The proposed method utilizes the power loop trace from the source terminal of bottom switch to circuit ground as the sensing trace. By measuring the sensing voltage and considering the frequency-dependent parasitic inductance and resistance of the sensing trace, the switching current is derived based on the Fourier series theory. The simulation verification is firstly performed by using LTspice, and shows consistent results. Then, to accurately measure the sensing voltage, the used voltage probe TPP1000 is carefully modeled for measurement compensation and correction. Finally, two double pulse test (DPT) boards are designed, one with coaxial current shunt and the other without coaxial current shunt. Through DPT experiment, the accuracy of the proposed method with almost no insertion inductance is verified.

Improved SiC MOSFET Model Considering Channel Dynamics of Transfer Characteristics

An improved SiC MOSFET model is proposed in this article, which predicts the dynamics accurately in the wide operation range of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . The temperature-sensitive effect (TSE), the short channel effect (SCE), and the interface state effect are comprehensively taken into consideration in the modeling of the transfer characteristics. A dynamic test platform of transfer characteristics is designed to extract data better than the datasheet. The turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> processes of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> are decoupled, and the nonlinear interterminal capacitances are also modeled thoroughly. To verify the convergence and accuracy of the proposed model, a 400 V/30 A double pulse test is fulfilled, and the complex converters are also simulated with the proposed model. The results show that the proposed model has good convergence and accuracy in predicting the switching trajectory of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> , which would be favorable for observing the dynamics in the high-speed switching processes of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> .

An Active Gate Driver of SiC MOSFET Module Based on PCB Rogowski Coil for Optimizing Tradeoff Between Overshoot and Switching Loss

The superior characteristics of the silicon carbide metal-oxide-semiconductor field-effect transistor (SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ) allow its wide use for improving the efficiency and power density of power electronic systems. However, the higher switching speed exacerbates the problems of overshoot, oscillation, and electromagnetic interference (EMI), which need to be properly addressed. In this article, a novel stage-detection closed-loop active gate driver (AGD) based on the printed-circuit-board (PCB) Rogowski Coil is proposed for optimizing the switching performance of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. And its stage identification threshold design can weaken the influence of the varying nonlinear parameters, especially for the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> process. First, the gate driver trajectory and the switching process of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> are analyzed. The optimal driver parameter dynamic configuration among the existing stage-control schemes is defined and unified, which aims to optimize the tradeoff between the overshoot and switching loss. Then, the parameter design of the PCB Rogowski Coil is illustrated. And the operation principle and working process of the proposed AGD are introduced. Finally, the performance of the proposed AGD and the effectiveness of the stage-control schemes are verified in the double-pulse test under different conditions. The experimental results show that the proposed AGD can not only reduce the overshoot and suppress the oscillation but also optimize the compromise of the switching loss and switching time.

Compact-Interleaved Packaging Method of Power Module With Dynamic Characterization of 4H-SiC MOSFET and Development of Power Electronic Converter at Extremely High Junction Temperature

Due to the outstanding material properties, silicon carbide (SiC) power device is the most promising alternative to silicon devices and can work at higher junction temperature. However, existing packaging technologies obstruct the use of SiC devices at high temperature and impede the continued exploration of SiC devices in high-temperature applications. This article proposes a novel hermetic metal packaging method called compact-interleaved package. The compact-interleaved power module handles the mentioned problems from three key considerations: packaging parasitic parameters, direct electrode measurement structure, and packaging materials. Based on the elaborate high-temperature double pulse test platform, dynamic characteristics of 1.2-kV/13-mΩ 4H-SiC power <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> are studied under the condition of extremely high junction temperature (up to 550 °C) and extremely high switching speed (about 3 kA/μs). The dynamic characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> are theoretically analyzed and verified by experimental measurements. Compared with other SiC bipolar devices, SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> maintains outstanding dynamic characteristics at extremely high temperatures and has an optimal operating high-temperature range. Finally, this article demonstrates an extreme-high-temperature power electronic converter to verify the superiority of the packaging method, and also proves the extreme-high-temperature power converting capability of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> .