Double-precision Floating-point Arithmetic Research Articles

Computation of parabolic cylinder functions having complex argument

Numerical methods for the computation of the parabolic cylinder function U(a,z) for real a and complex z are presented. The main tools are recent asymptotic expansions involving exponential and Airy functions, with slowly varying analytic coefficient functions involving simple coefficients, and stable integral representations; these two main methods can be complemented with Maclaurin series and a Poincaré asymptotic expansion. We provide numerical evidence showing that the combination of these methods is enough for computing the function with 5×10−13 relative accuracy in double precision floating point arithmetic.

Computation of the confluent hypergeometric function U(a,b,x) and its derivative for positive arguments

An algorithm and a MATLAB implementation for computing the Kummer function U(a,b,x) and its derivative is given in this paper. The algorithm is efficient and accurate. Numerical tests show that the MATLAB algorithm allows the computation of the function with sim 10^{-14} relative accuracy in the parameter region (a,b,x) ∈ (0,500) × (0,500) × (0,1000) in double-precision floating point arithmetic.

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

Evolution of the Graphics Processing Unit (GPU)

Graphics processing units (GPUs) power today’s fastest supercomputers, are the dominant platform for deep learning, and provide the intelligence for devices ranging from self-driving cars to robots and smart cameras. They also generate compelling photorealistic images at real-time frame rates. GPUs have evolved by adding features to support new use cases. NVIDIA’s GeForce 256, the first GPU, was a dedicated processor for real-time graphics, an application that demands large amounts of floating-point arithmetic for vertex and fragment shading computations and high memory bandwidth. As real-time graphics advanced, GPUs became programmable. The combination of programmability and floating-point performance made GPUs attractive for running scientific applications. Scientists found ways to use early programmable GPUs by casting their calculations as vertex and fragment shaders. GPUs evolved to meet the needs of scientific users by adding hardware for simpler programming, double-precision floating-point arithmetic, and resilience.

Towards a Bio-Inspired Real-Time Neuromorphic Cerebellum.

This work presents the first simulation of a large-scale, bio-physically constrained cerebellum model performed on neuromorphic hardware. A model containing 97,000 neurons and 4.2 million synapses is simulated on the SpiNNaker neuromorphic system. Results are validated against a baseline simulation of the same model executed with NEST, a popular spiking neural network simulator using generic computational resources and double precision floating point arithmetic. Individual cell and network-level spiking activity is validated in terms of average spike rates, relative lead or lag of spike times, and membrane potential dynamics of individual neurons, and SpiNNaker is shown to produce results in agreement with NEST. Once validated, the model is used to investigate how to accelerate the simulation speed of the network on the SpiNNaker system, with the future goal of creating a real-time neuromorphic cerebellum. Through detailed communication profiling, peak network activity is identified as one of the main challenges for simulation speed-up. Propagation of spiking activity through the network is measured, and will inform the future development of accelerated execution strategies for cerebellum models on neuromorphic hardware. The large ratio of granule cells to other cell types in the model results in high levels of activity converging onto few cells, with those cells having relatively larger time costs associated with the processing of communication. Organizing cells on SpiNNaker in accordance with their spatial position is shown to reduce the peak communication load by 41%. It is hoped that these insights, together with alternative parallelization strategies, will pave the way for real-time execution of large-scale, bio-physically constrained cerebellum models on SpiNNaker. This in turn will enable exploration of cerebellum-inspired controllers for neurorobotic applications, and execution of extended duration simulations over timescales that would currently be prohibitive using conventional computational platforms.

Mixed-precision iterative refinement using tensor cores on GPUs to accelerate solution of linear systems.

Double-precision floating-point arithmetic (FP64) has been the de facto standard for engineering and scientific simulations for several decades. Problem complexity and the sheer volume of data coming from various instruments and sensors motivate researchers to mix and match various approaches to optimize compute resources, including different levels of floating-point precision. In recent years, machine learning has motivated hardware support for half-precision floating-point arithmetic. A primary challenge in high-performance computing is to leverage reduced-precision and mixed-precision hardware. We show how the FP16/FP32 Tensor Cores on NVIDIA GPUs can be exploited to accelerate the solution of linear systems of equations Ax = b without sacrificing numerical stability. The techniques we employ include multiprecision LU factorization, the preconditioned generalized minimal residual algorithm (GMRES), and scaling and auto-adaptive rounding to avoid overflow. We also show how to efficiently handle systems with multiple right-hand sides. On the NVIDIA Quadro GV100 (Volta) GPU, we achieve a performance increase and 5× better energy efficiency versus the standard FP64 implementation while maintaining an FP64 level of numerical stability.

Simudo: a device model for intermediate band materials

We describe Simudo, a free Poisson/drift-diffusion steady state device model for semiconductor and intermediate band materials, including self-consistent optical absorption and generation. Simudo is the first freely available device model that can treat intermediate band materials. Simudo uses the finite element method (FEM) to solve the coupled nonlinear partial differential equations in two dimensions, which is different from the standard choice of the finite volume method in essentially all commercial semiconductor device models. We present the continuous equations that Simudo solves, show the FEM formulations we have developed, and demonstrate how they allow robust convergence with double-precision floating point arithmetic. With a benchmark semiconductor pn junction device, we show that Simudo has a higher rate of convergence than Synopsys Sentaurus, converging to high accuracy with a considerably smaller mesh. Simudo includes many semiconductor phenomena and parameters and is designed for extensibility by the user to include many physical processes.

FPGA Implementation of Double Precision Floating Point Arithmetic Unit

Every computer has a floating point processor or a dedicated accelerator that fulfils the requirements of precision using detailed floating point arithmetic. The main applications of floating points today are in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional audio. Floating point representation can support a much wider range of values than fixed point representation. In this design the complex logic operations which consist of various multiple numbers of stages are converted into single stage implementation. Once the inputs are applied to the input terminals the final output is obtained at the output terminals there are no intermediate stages. So now the input take less time to reach at output due to single stage implementation and the number of flip flops and other intermediate required circuits are less as a result the area require is less in the presented design called high throughput design. All four individual units addition, subtraction, multiplication and division are designed using Verilog and than combined into one single unit. The code is dumped into low cost Spartan 6 FPGA.

Double Precision Floating Point Arithmetic Unit Implementation- A Review

Double Precision Floating Point Arithmetic Unit Implementation- A Review

Numerically stable formulas for a particle-based explicit exponential integrator

Numerically stable formulas are presented for the closed-form analytical solution of the X-IVAS scheme in 3D. This scheme is a state-of-the-art particle-based explicit exponential integrator developed for the particle finite element method. Algebraically, this scheme involves two steps: (1) the solution of tangent curves for piecewise linear vector fields defined on simplicial meshes and (2) the solution of line integrals of piecewise linear vector-valued functions along these tangent curves. Hence, the stable formulas presented here have general applicability, e.g. exact integration of trajectories in particle-based (Lagrangian-type) methods, flow visualization and computer graphics. The Newton form of the polynomial interpolation definition is used to express exponential functions of matrices which appear in the analytical solution of the X-IVAS scheme. The divided difference coefficients in these expressions are defined in a piecewise manner, i.e. in a prescribed neighbourhood of removable singularities their series approximations are computed. An optimal series approximation of divided differences is presented which plays a critical role in this methodology. At least ten significant decimal digits in the formula computations are guaranteed to be exact using double-precision floating-point arithmetic. The worst case scenarios occur in the neighbourhood of removable singularities found in fourth-order divided differences of the exponential function.

Electromagnetic Problems Requiring High-Precision Computations

An overview of the applications of multiple-precision arithmetic in CEM was presented in this paper for the first time. Although double-precision floating-point arithmetic is sufficient for most scientific computations, there is an expanding body of electromagnetic problems requiring multiple-precision arithmetic. Software libraries facilitating these computations were described, and investigations requiring multiple-precision arithmetic were presented. In particular, numerical-precision issues were demonstrated based on the example of the discrete Green's function. Finally, some open problems in electromagnetics were pointed out for further investigations.

High Performance and Fault Tolerance Double Precision Floating Point Arithmetic Units

High Performance and Fault Tolerance Double Precision Floating Point Arithmetic Units

VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique

The double-precision floating-point arithmetic, specifically multiplication, is a widely used arithmetic operation for many scientific and signal processing applications. In general, the double-precision floating-point multiplier requires a large 53×53 mantissa multiplication in order to get the final result. This mantissa multiplication exists as a limit on both area and performance bounds of this operation. This paper presents a novel way to reduce this large multiplication. The proposed approach in this paper allows to use less amount of multiplication hardware compared to the traditional method. The multiplication is done by using Karatsuba technique. This design is specifically targeting Field Programmable Gate Array (FPGA) platforms, and it has also been evaluated on ASIC flow. The proposed module gives excellent performance with efficient use of resources. The design is fully compatible with the IEEE standard precision. The proposed module has shown a better performance in comparison with the best reported multipliers in the literature.

Evaluation of the Stretch S6 Hybrid Reconfigurable Embedded CPU Architecture for Power-Efficient Scientific Computing

Embedded CPUs typically use much less power than desktop or server CPUs but provide limited or no support for floating-point arithmetic. Hybrid reconfigurable CPUs combine fixed and reconfigurable computing fabrics to balance better execution performance and power consumption. We show how a Stretch S6 hybrid reconfigurable CPU (S6) can be extended to natively support double precision floating-point arithmetic. For lower precision number formats, multiple parallel arithmetic units can be implemented. We evaluate if the superlinear performance improvement of floating-point multiplication on reconfigurable fabrics can be exploited in the framework of a hybrid reconfigurable CPU. We provide an in-depth investigation of data paths to and from the S6 reconfigurable fabric and present peak and sustained throughput as a function of wide registers used and total operand size. We demonstrate the effect of the given interface when using a floating-point fused multiply-accumulate (FMA) SIMD unit to accelerate the LINPACK benchmark. We identify a mismatch between the size of the S6s reconfigurable fabric and the available interface bandwidth as the major bottleneck limiting performance which makes it a poor choice for scientific workloads relying on native support for floating-point arithmetic.

MrBayes on a Graphics Processing Unit

Bayesian phylogenetic inference can be used to propose a 'tree of life' for a collection of species whose DNA sequences are known. While there are many packages available that implement Bayesian phylogenetic inference, such as the popular MrBayes, running these programs poses significant computational challenges. Parallelized versions of the Metropolis coupled Markov chain Monte Carlo (MC³) algorithm in MrBayes have been presented that can run on various platforms, such as a graphics processing unit (GPU). The GPU has been used as a cost-effective means for computational research in many fields. However, until now, some limitations have prevented the GPU from being used to run MrBayes MC³ effectively. We give an appraisal of the possibility of realistically implementing MrBayes MC³ in parallel on an ordinary four-core desktop computer with a GPU. An earlier proposed algorithm for running MrBayes MC³ in parallel on a GPU has some significant drawbacks (e.g. too much CPU-GPU communication) which we resolve. We implement these improvements on the NVIDIA GeForce GTX 480 as most other GPUs are unsuitable for running MrBayes MC³ due to a range of reasons, such as having insufficient support for double precision floating-point arithmetic. Experiments indicate that run-time can be decreased by a factor of up to 5.4 by adding a single GPU (versus state-of-the-art multicore parallel algorithms). We can also achieve a speedup (versus serial MrBayes MC³) of more than 40 on a sufficiently large dataset using two GPUs. GPU MrBayes (i.e. the proposed implementation of MrBayes MC³ for the GPU) is available from http://mrbayes-gpu.sourceforge.net/.

GPU-accelerated indirect boundary element method for voxel model analyses with fast multipole method

An indirect boundary element method (BEM) that uses the fast multipole method (FMM) was accelerated using graphics processing units (GPUs) to reduce the time required to calculate a three-dimensional electrostatic field. The BEM is designed to handle cubic voxel models and is specialized to consider square voxel walls as boundary surface elements. The FMM handles the interactions among the surface charge elements and directly outputs surface integrals of the fields over each individual element. The CPU code was originally developed for field analysis in human voxel models derived from anatomical images. FMM processes are programmed using the NVIDIA Compute Unified Device Architecture (CUDA) with double-precision floating-point arithmetic on the basis of a shared pseudocode template. The electric field induced by DC-current application between two electrodes is calculated for two models with 499,629 (model 1) and 1,458,813 (model 2) surface elements. The calculation times were measured with a four-GPU configuration (two NVIDIA GTX295 cards) with four CPU cores (an Intel Core i7-975 processor). The times required by a linear system solver are 31 s and 186 s for models 1 and 2, respectively. The speed-up ratios of the FMM range from 5.9 to 8.2 for model 1 and from 5.0 to 5.6 for model 2. The calculation speed for element-interaction in this BEM analysis was comparable to that of particle-interaction using FMM on a GPU.

Design of Bowing-Activity Monitoring and Automatic Detection System Using 3-Axis Accelerometer

Abstract - In this paper, a new reliable portable activity monitoring device implemented with the buddhist-style bowing activity and walking step detection algorithm, is presented. In order to monitor the bowing and walking activities, miniaturized 3-axis accelerometer sensor with the sensitivity of 800 mV/g was used. After initial signal conditioning, vector magnitude of accelerometer signals was calculated. Syntactic peak detection method was used in order to feature points. All signal processing algorithms were implemented in ultra-low power microcontroller MSP430 with double precision floating point arithmetic. For evaluation, 19 young man(24.22±5.22 yrs) and woman(22.28±2.72 yrs) were involved. The accuracy of the proposed algorithms were 98.91%(±0.011) for walking step detection and 98.25%(±0.023) for buddhist-style bowing activity. Comparing to the commercialized pedometer accuracy, 87.1%(±0.058), the proposed walking step detection algorithms show more reliable accuracy. Key Words : 108 Bows, Pedometer, Walking Step, Bowing Activity, Wearable Monitor † 교신저자, 정회원 : 건국대 의료생명대 의학공학부 조교수, 건국대 의공학실용기술연구소・공박E-mail : jwlee95@kku.ac.kr* 정 회 원 : 건국대학교 의학공학부 박사과정** 비 회 원 : 경희대학교 체육대학 교수・체육과학박사*** 비 회 원 : (주)지우솔루션 기술연구소 접수일자 : 2010년 4월 26일 최종완료 : 2010년 5월 18일

FPGA implementation of adaptive segmentation for non-stationary biomedical signals

A novel field programmable gate array (FPGA) implementation of adaptive segmentation for non-stationary biomedical signals is presented. The design uses Simulink-to-FPGA methodology and has been successfully implemented onto Xilinx Virtex II Pro device. The implementation is based on the recursive least-squares lattice (RLSL) algorithm using double-precision floating-point arithmetic and is programmable for users providing data length, system order and threshold selection functions. The implemented RLSL design provides very good performance in obtaining accurate conversion factor values with a mean correlation above 99% and detecting segment boundaries with high accuracy for both synthesised and real-world biomedical signals.

Development of Simplified Solutions for Modeling Recession in Basins

In irrigation basins the decrease in the gradient of the water-surface elevation following inflow cutoff often leads to reduced rate of convergence, increased computational time, and reduced robustness of the numerical solutions of the recession phase. As the water surface levels off, the underlying physical problem simplifies, thus allowing the use of highly accurate yet simple alternate solutions to the full-numerical solution of the zero-inertia equations. For level basins, the simplification involves treating the stream as a static pool, in which water level only falls in response to infiltration. Graded basins may require partitioning the stream into a flowing and static pool, before water-surface eventually levels off over the entire stream length. Implementation of these solutions enhances computational efficiency and robustness of surface irrigation models without a concomitant loss of accuracy. This paper discusses numerical problems related to the recession phase computation in basins and proposes simplified and robust, yet highly accurate solutions. A comparison of the recession trajectories and final infiltration profiles predicted by the full-numerical solution of the zero-inertia equations, obtained by using double-precision floating-point arithmetic, and the simplified alternate solutions, which is robust enough to be implemented over a range of hardware-software capabilities, show that the two approaches yield essentially identical results. Finally, the general validity of the proposed solutions is tested by comparing predictions of recession trajectories and infiltration profiles with those obtained using a surface irrigation hydraulic model, SRFR.

Plane wave decomposition in the unit disc: Convergence estimates and computational aspects

This paper deals with the numerical simulation of time-harmonic wave fields using progressive plane waves. It is shown that a plane wave travelling in arbitrary direction can be numerically recovered with an accuracy of the order of the machine precision with a collocation formulation and the square root of the machine precision with a least-square formulation. However, strongly evanescent and nearly singular wave fields cannot be properly recovered with standard double-precision floating-point arithmetic. Some of the ideas are applied to the elastic wave equation and a simple optimization algorithm is proposed to find a good compromise between the accuracy and the number of plane waves.