FPGA Implementation of Double Precision Floating Point Arithmetic Unit

Abstract

Every computer has a floating point processor or a dedicated accelerator that fulfils the requirements of precision using detailed floating point arithmetic. The main applications of floating points today are in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional audio. Floating point representation can support a much wider range of values than fixed point representation. In this design the complex logic operations which consist of various multiple numbers of stages are converted into single stage implementation. Once the inputs are applied to the input terminals the final output is obtained at the output terminals there are no intermediate stages. So now the input take less time to reach at output due to single stage implementation and the number of flip flops and other intermediate required circuits are less as a result the area require is less in the presented design called high throughput design. All four individual units addition, subtraction, multiplication and division are designed using Verilog and than combined into one single unit. The code is dumped into low cost Spartan 6 FPGA.