Abstract
A floating-point unit (FPU) is a part of a computer system specially designed to carry out operations on floating point numbers. Floating point representation can support a much wider range of values than fixed point representation. This paper presents high speed FPGA implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, division functions on 32-bit operands that use the IEEE 754-2008 standard. The amount of hardware used in the single architecture is found to be less than the sum of hardware required in individual floating point units. All four individual units are implemented using VHDL and than one single unit is designed named floating point unit which can perform all the four operations. The code is dumped into vertex-5 FPGA.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IOSR Journal of Electronics and Communication Engineering
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
