Double Patterning Techniques Research Articles

B-open Defect: A Novel Defect Model in FinFET Technology

This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same gates, the electrical effects of the bridge and the open combine and exhibit a new specific electrical behavior; we call this new defect behavior a b-open. As a consequence, existing test generation methodologies may miss defect detection. The electrical behavior of the b-open defect is first analyzed graphically and then validated through extensive SPICE simulations. The test pattern conditions to detect the b-open defect are finally determined, and it is shown that the b-open defect requires specific test generation.

High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch

A hexagonal honeycomb magnetic tunneling junction array with 72 nm pitch and 30 nm MgO critical dimension was successfully fabricated on a 1× nm dynamic random access memory platform by using a mature dynamic random access memory patterning solution and ion beam etch. To our knowledge, both pitch size and critical dimension size are the world’s smallest ones for industrial magnetic tunneling junction arrays. To obtain such a high density and small sized magnetic tunneling junction array, a cross self-aligned double patterning technique, a triple layer hard mask scheme, and an optimized ion beam etch condition were adopted. During the optimization of the ion beam etch process, the dependence of a magnetic tunneling junction pillar profile on ion beam etch parameters for a high density hexagonal magnetic tunneling junction array has also been systematically studied. The depth of oxide recess and the magnetic tunneling junction sidewall angle increased with the ion beam etch amount, while magnetic tunneling junction critical dimension and hard mask remainder thickness decreased with increasing ion beam etch amount.

Middle of Line (MoL) Cleaning Challenges in Sub-20nm Node Device Manufacturing

In advanced technology nodes (sub 20nm), the gate & active contact architecture has become very complex. This architecture not only introduced new materials but also integrated additional patterning mask layers. This necessitated a separate Middle of Line (MoL) zone whereas conventionally contact integration used to be a Front End of Line (FEoL) process. This paper discusses wet cleaning challenges in MoL that were unforeseen with conventional contact architecture. Typical chemistries such as Sulfuric Peroxide Mixture (SPM), dilute Hydrofloric Acid (dHF), Aqua Regia, Standard Clean 1 (SC1), etc. that were used for contact cleaning or in salicidization process are found to be too aggressive due to smaller process window, shrinking Critical Dimensions (CD), and other challenges arising from overall tighter tolerances. As a result of device scaling, most of the MoL mask patterning is done with immersion lithography and double patterning techniques such as Litho-Etch Litho-Etch (LELE) are also needed. Immersion lithography is very sensitive to pre-litho backside and frontside particles which make pre-litho cleaning in MoL very critical as well. Also due to lack of high aspect ratio features in MoL (mostly contact holes), physical particle removal techniques such as droplet spray and MegaSonic can be very effectively used to achieve higher Particle Removal Efficiency (PRE). This paper summarizes such different scenarios & related challenges.

Applications for Surface Engineering Using Atomic Layer Etching - Invited Paper

Over the course of the past few years, the semiconductor industry has continued to invent and innovate profoundly to adhere to Moore’s Law and Dennard scaling. At each of the technology nodes starting with 45nm, new materials and integration techniques, such as high-K & metal gates, double patterning techniques, and now 3D FinFet / Trigate device geometries are being introduced in order to maintain device performance. This places a large burden on unit process development to accommodate and deliver advanced process capability and is growing the need for the ultimate etch solution: etching with atomic layer precision. Atomic layer etching is a promising path to answer the processing demands of thin high mobility channel devices on the angstrom scale. Self-limiting reactions, discrete reaction & activation steps, or extremely low ion energy etch plasmas are some of the pathways being pursued for precise sub-nanometer material removal. In this invited paper, previously published in SPIE, the ability to achieve atomic layer etch precision is reviewed in detail for a variety of material sets and implementation methods. For a cyclic approach most similar to a reverse ALD scheme, the process window to achieve a truly self-limited atomic layer etch process is identified and the limitations as a function of controlling the adsorption step, the irradiation energy, and the reaction process are examined. Alternative approaches, including processes to enable pseudo-ALE precision, are then introduced and results from their application investigated. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. Significant improvements however were obtained when applying PE-ALE approaches to small pitch patterns. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.

Spectral analysis of sidewall roughness during resist-core self-aligned double patterning integration

Double patterning technology has now proved its efficiency to go beyond the standard lithographic printing limits and address the resolution requirements of the sub-20 nm technological node. However, some data are still lacking regarding the characterization of line edge/width roughness (LER/LWR) in such integration. In this work, a detailed spectral analysis of the sidewall roughness evolution during a resist-core self-aligned double patterning (SADP) integration is presented. A 20 nm half-pitch SADP process using photoresist as the core material, and SiO2 deposited by plasma enhanced atomic layer deposition as the spacer material is developed. The LER and LWR have been characterized at each technological step involved in the SADP process flow, using a power spectral density fitting method, which provides a full description of the sidewalls roughness with the estimation of noise-free roughness amplitude (σ), correlation length (ξ), and roughness exponent (α). Results show that the SADP process allows to decrease drastically the LWR and LER amplitudes down to 2.0 nm corresponding to a reduction of about 70% and 50%, respectively, compared to the initial resist patterns. Although the SADP concept generates two asymmetric populations of lines, the final features present similar LWR, LERleft, and LERright parameters. The study also highlights the effectiveness of the SADP concept to decrease critical dimension variation and low-frequency LWR components to values inferior to 1 nm, which is an outstanding improvement compared to other single or double patterning techniques. However, this work brings out that the deposition process is the key step to ensure successful resist-core SADP integration. It must not only be as conformal as possible but also preserve the square shape of the core material. It is shown that the resist lateral erosion occurring during the deposition step introduces some random resist sidewalls angles that contribute to the formation of short range roughness during the spacer etching transfer, resulting in residual LWR mainly composed of high-and medium-frequency components. Contrary to LWR, the beneficial impact of the conformal spacer deposition on low-frequency roughness components has rather no effect on LER. The LER parameters after spacer etching mainly depend on the core ones prior to deposition. LER low-frequency components remain a key issue to address for an optimized integration.

Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor

Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor

A master-mold fabrication by electron beam lithography followed by nanoimprinting and self-aligned double patterning

As a new scheme of master-mold fabrication, a half pitch (hp) 12 nm line and space (L/S) pattern was fabricated from hp 24 nm L/S resist mandrels, which were prepared by electron beam (EB) writing as well as nanoimprinting, followed by the self-aligned double-patterning (SADP) technique. It was observed that the line width roughness (LWR) was reduced and improved by single and multiple nanoimprintings in the new scheme of the master-mold fabrication to make hp 24 nm resist mandrels. We have studied the phenomena and revealed that the resist pattern of nanoimprinting had sharper and smoother shoulders and bottom edges in cross section than those of the EB resist. These shoulder shapes of nanoimprinting seemed to be reflected in its LWR improvement. The new scheme has advantages of resolution enhancement and better pattern quality of LWR on a master mold for nanoimprint lithography, in comparison with conventional optical and EB lithography technologies.

Fabrication and characterization of a deep ultraviolet wire grid polarizer with a chromium-oxide subwavelength grating.

A wire grid polarizer comprised of chromium oxide is designed for a micro-lithography system using an ArF excimer laser. Optical properties for some material candidates are calculated using a rigorous coupled-wave analysis. The chromium oxide wire grid polarizer with a 90 nm period is fabricated by a double-patterning technique using KrF lithography and dry etching. The extinction ratio of the grating is greater than 20 dB (100:1) at a wavelength of 193 nm. Differences between the calculated and experimental results are discussed.

The Challenges and Solutions of High-K First Dummy Gate Etch

In this work, we focused on the dummy gate etch process for high-k first process and firstly investigated two etch schemes with end-cut based double patterning technique. The pure hard-mask scheme is proven to be superior from the point of view of the aspect ratio, the control of the selectivity of ODL over poly-Si and the impact of ODL removal on HK capping layer and silicon substrate. Compared with the traditional poly-Si gate etch, HK capping layer can serve as more reliable etch stop layer. However, the extra steps dedicated to HK and its capping layer affect the bottom profile of poly-Si gate, ending up with notched bottom profile. Treatment after poly-Si etch has been demonstrated to remarkably alleviate such impact. Besides, we also demonstrated different sidewall profile of HK and its capping layer, which can affect final transistor performance and needs precisely control.

Obtaining nanoimprint template gratings with 10 nm half-pitch by atomic layer deposition enabled spacer double patterning

A strategy for fabricating nanoimprint templates with sub-10 nm line and 20 nm pitch gratings is demonstrated, by combining electron beam lithography and atomic layer deposition. This is achieved through pitch division using a spacer double-patterning technique. The nanostructures are then replicated using step-and-repeat ultra-violet assisted nanoimprint lithography.

Scanning interference evanescent wave lithography for sub-22-nm generations

Large field, ultra-high numerical aperture (NA) lithography is desired in semiconductor manufacturing. We report progress in developing a scanning evanescent wave lithography (s -EWL) imaging head with a two-stage gap control system including a DC noise canceling air bearing, which houses an AC noise-canceling piezoelectric actuator. Various design aspects of the system, including gap detection, prism design, optical alignment, software integration, feedback actuation, and a scanning scheme have been developed to ensure sub-100-nm gap control. Experimental results have shown successful gap gauging with a gap noise root-mean-square (RMS) of 1.38 nm in static gap control, and 4.64 nm in linear scanning gap control. Integrating the prototype imaging head into a two-beam interferometer platform has demonstrated dynamic stepping imaging using fused silica and sapphire prisms, with potential NA values up to 1.85 (26-nm half-pitch). These results achieved with s -EWL provide a possible route to extend optical lithography to 16-nm generations and beyond when combined with double patterning techniques.

Application of double patterning technology to fabricate optical elements: Process simulation, fabrication, and measurement

Double patterning is an important technique for the improvement of spatial resolution in fabricated micro and nanostructures. In this paper, we investigated and applied the double patterning technique to fabricate diffractive optical elements. Simulations of multiple dry etch and film deposition steps were performed to study and optimize the vertical profiles of the fabricated patterns. Etch and deposition characteristics were varied to study their impact on the resulting vertical profile of the metal layers. The influence of the linewidth of the initial resist pattern and the process-induced tapering of the grating tops on the optical performance were investigated in particular. A variably shaped electron-beam lithography system was used for the fabrication of the initial resist pattern. The spatial frequency was then doubled by means of double patterning. Broadband aluminum and iridium wire grid polarizers were fabricated for applications down to the UV range with a feature size of 30 nm, a period of 100 nm, and a vertical aspect ratio of about 5:1. Optical measurements have confirmed the designed optical properties.

Toward 22 nm: fast and effective intrafield monitoring and optimization of process windows and critical dimension uniformity

ITRS lithography's stringent specifications for the 22 nm node are a major challenge for the semiconductor industry. With the EUV point insertion at 16 nm node, ArF lithography is expected to reach its fundamental limits. The prevailing view of holistic lithography methods, together with double patterning techniques, has targeted bringing lithography performance toward the 22 nm node (i.e., closer to the immersion scanner resolution limit) to an acceptable level. At this resolution limit, a mask is the primary contributor of systematic errors within the wafer intrafield domain. As the ITRS critical dimension uniformity (CDU) specification shrinks, it would be crucial to monitor the mask static and dynamic critical dimension (CD) changes in the fab, and use the data to control the intrafield CDU performance in a most efficient way. Furthermore, optimization and monitoring of process windows (PW) becomes more critical due to the presence of mask three-dimensional effects. This paper will present double patterning inter- and intrafield data, for CDU and PW monitoring and optimization, measured by Applied Materials' mask inspection and CD-SEM tools. Special emphasis was given to speed and effectiveness of the inspection for a production environment.

Double Patterning Using Multilayer Hard Mask Process with Perhydropolysilazane

A new technology called the double patterning (DP) process with ArF immersion lithography is one of the candidate fabrication technologies for 32-nm-node devices. Over the past few years, many studies have been conducted on techniques of the DP process. Among these technologies, the double Si hard mask (HM) process is thought to be the most applicable technology from the viewpoint of high technical applicability to 32-nm-node device fabrication. However, this process has a disadvantage in terms of cost performance compared with other DP technologies since these HMs are formed by the chemical vacuum deposition (CVD) method. In this study, we examined the DP process using a dual spin-on Si-containing layer without using the CVD method to improve process cost and process applicability. Perhydropolysilazane (PSZ) was used as one of the middle layers (MLs). PSZ changes to SiO2 through reaction with water by the catalytic action of amine in the baking step. Using PSZ and Si-BARC as MLs, we succeeded in fabricating a fine pattern by this novel DP technique. In this paper, the issues and countermeasures of the double HM technique using spin-on Si-containing layers will be reported.

Fabrication of Silicon Pillar with 25 nm Half Pitch Using New Multiple Double Patterning Technique

For the higher-density cells of next-generation semiconductor memories, many recent studies have focused on the vertical cell structure technology, which includes various performance merits such as small cell size, high drivability, and suitability for cell-stacked-type arrays. The authors developed a new method to fabricate 25 nm half pitch dense Si pillars that would be applicable to the fabrication of vertical cell devices. Using the proposed multiple double patterning techniques, 23.6 nm diameter, 114 nm height Si cylindrical pillars with a half pitch of 25 nm were fabricated. We confirmed the uniformity in a 300 mm wafer at 30 points, and its 3σ was only 1.7 nm. Moreover, we examined the presence of pillar collapse at arbitrarily selected chip dies for confirmation. Surprisingly, there was no pillar collapse within any of the inspected areas. From these verifications, we conclude that our proposed fabrication technique for slim Si pillars is now available.

Fabrication of Silicon Pillar with 25 nm Half Pitch Using New Multiple Double Patterning Technique

Fabrication of Silicon Pillar with 25 nm Half Pitch Using New Multiple Double Patterning Technique

Studying Photoresist Type for Sub-32nm Node Dense SRAM 2nd GT Layer

With continuous shrinking of device dimensions, high performance, dense SRAM cells design has become more challenging than before, patterning quality is also more sensitive to fluctuations in lithography process. This inevitably calls for more aggressive lithography process conditions in terms of the required resolution. The tradeoff between process window optimization for random logic gates and dense SRAM is not always straightforward, and it sometimes necessitates design rule and layout modifications. In particular, patterning the small tip-to-tip gap for dense SRAM cells at gate level becomes extremely challenging. By delinking patterning of SRAM tip-to-tip from other geometries, one can optimize the patterning processes independently at the expense of cost. This can be achieved through a special double patterning technique that employs a combination of double exposure and double etch (DE2).

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

We propose shift-trim double-patterning lithography (ST-DPL), a cost-effective double-patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double patterning (ST-DPL as well as standard DPL). 2× pitch relaxation being associated with a considerable area overhead, 1.8 × pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<; 0.3% cell-area overhead) and no more than 4.7% cell-area overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double patterning: 1) cuts mask-cost to nearly half; 2) reduces overlay errors between the two patterns; 3) alleviates the bimodal line-width distribution problem in double patterning; and 4) slightly enhances the throughput of critical-layer scanners.

Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique

The authors present a simple double patterning technique with I-line stepper to define nanoscale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-100-nm gate length. With this approach, polycrystalline silicon (poly-Si) gate with linewidth down to 80 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography. Moreover, ineffectiveness of end point detection in the second poly-Si gate definition is also addressed. For reliable process control in the second etching step, appropriate mask design is found to be essential. Finally, sub-100-nm MOSFETs with or without halo implemented symmetrically or asymmetrically are fabricated and characterized.

Important Challenge for Optical Lithography Extension utilizing Double Patterning Process

Lithographic scaling has been driven by improvements in wavelength and numerical aperture historically. In the semiconductor industry, the H2O base 192 immersion technique has still been main exposure tool combined with various low-k1 techniques, such like off-axis illumination, phase-shift mask and so on. The focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh′s definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for downward scaling and various device layouts utilizing SADP (Self-aligned Double patterning) mainly.