Double Patterning Techniques Research Articles

Lithographic Significance of Wafer Back Surface Nanotopography

Wafer topography plays a critical role in the performance of lithography at smaller nodes. The contribution of low to medium spatial frequency components of wafer topography to overlay error is currently a topic of interest within the lithography community, especially as double patterning techniques have reduced overlay error budgets by a factor of two. Nanotopography, comprised of the higher spatial frequency components of wafer topography can contribute to non-correctable errors (NCE) for the scanner. In this paper we use finite element analysis to investigate the transfer of back-surface nanotopography to the front surface as the wafer is chucked either on a pin chuck or a flat vacuum chuck. The results are found to be lithographically significant, suggesting that fabs may benefit from measuring back-surface nanotopography, and developing appropriate specs for incoming wafers.

Litho/Design Co-Optimization and Area Scaling for the 22-nm Logic Node

We present a comprehensive study of area scaling for 22nm-logic-node routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and double-patterning (DP) regimes. For each candidate route pitch (88-56nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel 'source/design optimization' technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

Integration of block copolymer directed assembly with 193 immersion lithography

An integration scheme of block copolymer directed assembly with 193 nm immersion lithography is presented. It is experimentally shown that a thin silicon nitride film can be used as an antireflective coating (ARC). With such an ARC, directed assembly of a block copolymer (BCP) to triple the feature density of a chemical pattern was demonstrated. A high quality of assembly was obtained over a large area, and pattern transfer feasibility was illustrated. The integration of feature density multiplication via directed assembly of a BCP with 193 nm immersion lithography provided a pattern quality that was comparable with existing double patterning techniques, suggesting that the process could be a promising candidate for extending the use of current 193 immersion lithography tools to higher pattern densities.

A simple method for sub-100 nm pattern generation with I-line double-patterning technique

We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal–oxide-semiconductor field-effect transistors. Excellent device characteristics were verified.

Deep-UV Technology for the Fabrication of Bragg Gratings on SOI Rib Waveguides

In this letter, we present a wafer level technology based on deep-ultraviolet lithography to fabricate Bragg gratings on silicon-on-insulator rib waveguides. The principle of the used double-patterning technique is presented, as well the influence of the process variation on the device performances. The fabricated Bragg gratings were characterized and compared to analogue structures patterned with electron-beam lithography.

High density submicron features using a laser pattern generator and double patterning

Line and space patterns have been fabricated in Si with periods as small as 1.3μm using a double patterning technique and an optical direct write tool. The pattern density of a single lithography step is shown to be limited by the proximity effect and that gratings with periods smaller than about 2.0μm are beyond the resolution of the 405nm wavelength laser direct write tool employed in these experiments. The lithography-etch–lithography-etch technique, which includes a highly selective reactive ion etch step, provides a robust way to create 4mm long gratings of 1.5μm period. Variations in this two step lithography process limit the practical minimum pitch for long gratings to about 1.4μm.

Efficient simulation and optimization of wafer topographies in double patterning

As the technology marches toward the 32-nm node and beyond in semiconductor manufacturing, double-patterning and double-exposure techniques are currently regarded as the potential candidates to produce lines and spaces and contact holes, respectively. We employ the Waveguide method, a rigorous electromagnetic field (EMF) solver, to investigate the impact of wafer topographies on two specific double-patterning techniques. At first, the topography effects induced by the first patterning on the second lithography process in a lithography-etch-lithography-etch process are demonstrated. A new methodology of the bottom antireflective coating optimization is proposed to reduce the impact of wafer topography on resist profiles. Additionally, an optical proximity correction (OPC) of the second lithography mask is demonstrated to compensate the wafer-topography-induced asymmetric deformations of line ends. Rigorous EMF simulations of lithographic exposures are also applied to investigate wafer-topography effects in a freezing process. The difference between the optical properties of the frozen (first) resist and the second resist potentially causes linewidth variations. Quantitative criteria for tolerable refractive index and extinction differences between the two resist materials are given. The described studies can be used for the optimizations of topographic waferstacks, the OPC of the second litho mask, and for the development of resist materials with appropriate optical properties.

Demonstration of 12 nm Resolution Fresnel Zone Plate Lens based Soft X-ray Microscopy

To extend soft x-ray microscopy to a resolution of order 10 nm or better, we developed a new nanofabrication process for Fresnel zone plate lenses. The new process, based on the double patterning technique, has enabled us to fabricate high quality gold zone plates with 12 nm outer zones. Testing of the zone plate with the full-field transmission x-ray microscope, XM-1, in Berkeley, showed that the lens clearly resolved 12 nm lines and spaces. This result represents a significant step towards 10 nm resolution and beyond.

Progress in Extending Immersion Lithography for the 32 nm Node and Beyond

Optical lithography has met the challenge of the Semiconductor Industry's increasing resolution and the tighter overlay requirements by progressively: increasing the optics numerical aperture; shortening the illumination wavelength; and supporting low-k factor processing. This trend continued with the wavelength being shortened to 13 nm for extreme ultraviolet (EUV) lithography tools, and with numerical apertures increased to 1.35 for water-based immersion lithography tools. Currently, water-based, 193 nm, immersion tools are capable of printing at <40 nm (half pitch) resolutions with <6 nm overlay accuracy. For the next lithographic nodes, water-based immersion lithography will be used with double patterning techniques, and this will pushdown to below the 32 nm node. The major challenges for the exposure tools are the tightening of the specifications required with double pattering, while dealing with shrinking process windows. The specifications requirements include increased throughput, tighter overlay, and tighter critical dimension control. New high-speed systems are being developed at ASML to meet these requirements. This paper reviews the possibility of using double patterning to extend immersion lithography tools, beyond the 32 nm node while production EUV lithography is coming on line.

A Cost Effective Spin on Sidewall Material Alternative to the CVD Sidewall Process

193nm immersion and Hyper NA lithography are used at 45nm and beyond. The next generation of lithography will use a new technology such as Double Pattering, EUV or EB. Double patterning is one of the currently acceptable technologies. Three common double pattern techniques are Litho-Etch-Litho-Etch (LELE), freezing, and sidewall (spacer) process. From a technical standpoint LELE is a very promising process, except for the second litho alignment. However, the cost of ownership will be very high because LELE will cost about twice as much as the current single litho patterning process. In order to build up a suitable double patterning technique, many device makers are developing unique processes. Two of these processes are freezing and sidewall. Flash memory makers are diligently investigating the sidewall process by CVD. This is because of the lack of a second litho alignment step, even with its high cost. The high cost of the CVD process can be reduced if a spin on material is used. One of the goals of this paper is to reduce the cost of ownership by using spin on coatings for the sidewall process. Currently we are investigating this approach to control the sidewall width, profile and other properties.

Resist charging effect in photomask: Its impact on pattern placement error and critical dimension

By the development of the double exposure technique or the double patterning technique, the pattern placement error of a photomask is interesting because of its impact on the size and position of wafer pattern. Among various sources to induce the pattern placement error, we have focused on the charging effect of the FEP-171 resist and have shown that the resist charging effect generates the pattern position error of a clear pattern and the critical dimension variation of a dark pattern. Based on experiment and simulation, we present quantitatively the dependence of position error on pattern density, pattern shape, and writing order. Furthermore, we have discussed the model to describe the charging effect and its agreement with experiment and the correction method to remove the resist charging effect.

Double patterning overlay budget for 45nm technology node single and double mask approach

Double patterning (double exposure and double etch) is definitely a viable solution for overcoming the physical resolution limit of k1=0.25 of imaging systems. This article presents the overlay budget for a double patterning technique using a 45nm technology node flash memory device with k1∼0.20 and 193nm dry lithography. Adopting double exposure, the final pattern is composed of two lithography patterns within the resolution capability of the exposure tool and then combined with the double etching processes. The photoetch photoetch approach creates the overlay between the two exposures which is the most critical issue to be addressed. This article presents the adopted scanner setup, mask requirements, and efficient overlay metrology setup in order to achieve the overlay roadmap of 6nm for the 45nm technology node.

Extreme ultraviolet lithography: A review

Extreme ultraviolet lithography (EUVL) was thoroughly reviewed over a broad range of topics, including history, tools, source, metrology, condenser and projection optics, resists, and masks. Since 1988, many studies on EUVL have been conducted in North America, Europe, and Japan, through state sponsored programs and industrial consortiums. To date, no “show stopper” has been identified, but challenges are present in almost all aspects of EUVL technology. Commercial alpha lithography step-and-scan tools are installed with full-field capability; however, EUVL power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 180W IF power, current tools can supply only approximately 55–62W. EUV IF power has been improved gradually from xenon- to tin-discharge-produced plasma or laser-produced plasma. EUVL resist has improved significantly in the last few years, with 25nm 1:1 line/space resolution being produced with approximately 2.7nm (3σ) line edge roughness. Actual adoption of EUVL will depend on the extension of current optical lithography, such as 193nm immersion lithography, combined with double patterning techniques. Mask fabrication and application technologies may be the most substantial challenges. Creating a defect-free EUVL mask is currently an obstacle to its application, although a combination of removable pellicle and thermophoretic protection may overcome nonpellicle challenge. Cost of ownership is a critical consideration for EUVL; nevertheless, it has been predicted that EUVL may be in pilot production at 32nm and in large-scale production at 22nm with the capability to extend to the next technology node.

Double-Patterning Technique Using Plasma Treatment of Photoresist

The double-patterning process was investigated for line-and-space (L/S) patterns of 65 nm half pitch [k1=0.286, 0.85-numerical aperture (NA) ArF dry system] by plasma treatment of photoresist (PR). The sequence of this patterning is exposure–plasma treatment–exposure–etching. Si thin-film passivation and HBr plasma treatment (HPT) were applied, and Si thin-film passivation is preferred to HPT in terms of intermixing prevention and etch selectivity. For planarization of the topographic surface, a thick bottom PR was coated on the pattern after the first exposure. Si thin-film passivation and the thick bottom PR enabled the second exposure to be separated from the first exposure. After the etching process was completed down to the nitride hardmask material, the L/S patterns of 65 nm half pitch were achieved at the full-chip level by virtue of the Si thin-film passivation and thick bottom PR. In the meantime, considering the layout characteristic and process flexibility, layout decomposition and the optical proximity correction (OPC) process were performed. Even though the 65 nm half pitch is defined to be such that k1=0.286, it is believed that this double patterning scheme we suggested can be applied at the minimum pitch over the theoretical limit below 0.25. Consequently, it is expected that the double-patterning technique (DPT) process will have an important role in the extremely low k1 lithography beyond the 32 nm node.

Impact of registration error of reticle on total overlay error budget

As the overlay specification decreases drastically, it is necessary to consider how the total overlay is influenced by each contributing factor. In particular, it is expected that the contribution on overlay error budget can be quantitatively analyzed in terms of the correlation among registration errors of the reticle. The reticle contribution of about 25% is assessed by the breakdown of the sources of overlay metrology uncertainty through the double exposure technique (DET) process. A positive correlation of around 0.7 mitigates the reticle contribution by 180%, compared to the uncorrelated case. In both DET and double patterning technique (DPT) processes, it is needed to positively correlate the registration errors among many reticles in order to decrease the reticle contribution. To maintain the gain of 180% due to positive correlation, the correlation coefficient requisite has to be increased it is difficult to achieve highly positive correlation among more than three reticles. From an integration po...