The Challenges and Solutions of High-K First Dummy Gate Etch

Abstract

In this work, we focused on the dummy gate etch process for high-k first process and firstly investigated two etch schemes with end-cut based double patterning technique. The pure hard-mask scheme is proven to be superior from the point of view of the aspect ratio, the control of the selectivity of ODL over poly-Si and the impact of ODL removal on HK capping layer and silicon substrate. Compared with the traditional poly-Si gate etch, HK capping layer can serve as more reliable etch stop layer. However, the extra steps dedicated to HK and its capping layer affect the bottom profile of poly-Si gate, ending up with notched bottom profile. Treatment after poly-Si etch has been demonstrated to remarkably alleviate such impact. Besides, we also demonstrated different sidewall profile of HK and its capping layer, which can affect final transistor performance and needs precisely control.