Double Heterostructure Bipolar Transistors Research Articles

Transferred-Substrate InP/GaAsSb Heterojunction Bipolar Transistor Technology With <inline-formula> <tex-math notation="LaTeX">${f}_{\text{max}}$ </tex-math> </inline-formula> ~ 0.53 THz

We report on the realization mymargin of transferred-substrate InP/GaAsSb double heterostructure bipolar transistors in a terahertz monolithic integrated circuit process. Transistors with 0.4- $\mu \text{m}$ -wide single emitters reached unilateral gain cutoff frequencies of around 530 GHz with simultaneous current gain cutoff frequencies above 350 GHz. Extrinsic collector capacitance is effectively reduced in the transfer-substrate process. In combination with the high collector breakdown voltage in the InP/GaAsSb heterobipolar transistor structure of 5 V, this process is amenable to analog power applications at millimeter (mm-wave) and sub-mm-wave frequencies. We demonstrate reliable extraction procedures for unilateral gain and current gain cutoff frequencies.

A +14.2 dBm, 90–140 GHz Wideband Frequency Tripler in 250-nm InP DHBT Technology

A single-chip active frequency tripler circuit with output at F-band (90–140 GHz) is presented. A common-emitter transistor stage with input and output matching circuits is used to produce the third harmonic, followed by a five-pole band-pass filter and a wideband four-stage power amplifier to amplify and increase the output power. The circuit is implemented in a 250-nm InP double-heterostructure bipolar transistor technology with ft/fmax 350/650 GHz, respectively. The chip achieves a peak output power of 14.2 dBm from 99 to 126 GHz at 2-dBm input power and conversion gain of 13 dB at −2-dBm input power. The measured 3-dB output bandwidth is 51 GHz from 90 to 141 GHz which corresponds to 44.2% relative bandwidth. It demonstrates up to 23-dBc rejection ratio of the first and the second harmonics. The dc power consumption is 156 mW at 2-dBm input power. The chip size is $0.9 \times 0.96\,\,\text {mm}^{{2}}$ including pads and achieves a power efficiency of 16.7%.

Multifinger Indium Phosphide Double-Heterostructure Transistor Circuit Technology With Integrated Diamond Heat Sink Layer

The RF power output of scaled subterahertz and terahertz indium phosphide double-heterostructure bipolar transistors (InP DHBTs) is limited by the thermal device resistance, which increases with the geometrical frequency scaling of these devices. We present a diamond thin-film heat sink process aimed at the efficient removal of the heat generated in submicrometer InP HBTs. The thin-film diamond is integrated in a wafer bond process. Vertical connections are facilitated by plasma-processed contact holes through the diamond layer, metallized with electroplated gold. The process is suitable for monolithic circuit integration, amenable to the realization of high-power analog circuits in the millimeter-wave region and beyond. The thermal resistance of double-finger transistors with a 0.8- $\mu \text{m}$ emitter width could be reduced to 0.7 K/mW, while reaching the gain cutoff frequencies of $f_{T}=360$ GHz and $f_{\mathrm {max}}=350$ GHz. An integrated two-stage power amplifier with four-way power combining fabricated in this technology exhibited 20-dBm power output at 90 GHz with a bandwidth of 10 GHz.

A THz InGaAs/InP double heterojunction bipolar transistor with fmax = 325 GHz and BVCBO = 10.6 V

A common-base four finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and fabricated using triple mesa structure and planarization technology. All processes are on 3-inch wafers. The area of each emitter finger is 1 × 15 μm2. The maximum oscillation frequency (fmax) is 325 GHz and the breakdown voltage BVCBO is 10.6 V, which are to our knowledge both the highest fmax and BVCBO ever reported for InGaAs/InP DHBTs in China. The high speed InGaAs/InP DHBT with a high breakdown voltage is promising for submillimeter-wave and THz electronics.

Composite-Collector InGaAs/InP Double Heterostructure Bipolar Transistors with Current-Gain Cutoff Frequency of 242 GHz

To eliminate the conduction band spike at the base-collector interface, an InP/InGaAs double heterostructure bipolar transistor (DHBT) with an InGaAsP composite collector is designed and fabricated using the conventional mesa structure. The DHBT with emitter area of 1.6 × 15 μm2 exhibits current-gain cutoff frequency ft = 242 GHz at the high collector current density Jc = 2.1 mA/μm2, which is to our knowledge the highest ft reported for the mesa InP DHBT in China. The breakdown voltage in common-emitter configuration is more than 5 V. The high-speed InP/InGaAs DHBT with high current density is very suitable for the application in ultra high-speed digital circuits.

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1×15μm2. The breakdown voltage was more than 7V, the current could be more than 100mA. The maximum output power can be more than 80mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305GHz at IC=50mA and VCB=1.5V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.

High-Speed InGaAs/InP Double Heterostructure Bipolar Transistor with High Breakdown Voltage

We design and fabricate an InGaAs/InP double heterostructure bipolar transistor (DHBT). The spike of the conduction band discontinuity between InGaAs base and InP collector is successfully eliminated by insertion of an InGaAs layer and two InGaAsP layers. The current gain cutoff frequency and maximum oscillation frequency are as high as 155 and 144 GHz. The breakdown voltage in common-emitter configuration is more than 7 V. The high cutoff frequency and high breakdown voltage make high-speed and high-power circuits possible.

High-Gain Arsenic-Rich n-p-n InP/GaAsSb DHBTs With $F_{T} ≫ \hbox{420}\ \hbox{GHz}$

Type-II n-p-n InP/GaAsSb/InP double heterostructure bipolar transistors (DHBTs) that are fabricated by optical lithography with a 0.6 times 5 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> emitter on a 20-nm compositionally uniform GaAsSb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> , carbon-doped base with x = 0.60 and a 75-nm InP collector show current-gain cutoff frequencies as high as 423 GHz at 10 mA/mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and feature a BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> = 4 V. The pseudomorphic As-rich InP/GaAsSb DHBTs feature a high maximum dc current gain of > 160, owing to the reduction of the type-II conduction band discontinuity DeltaE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and the associated recombination at the InP/GaAsSb emitter-base interface. This brief demonstrates that the InP/GaAsSb DHBT technology can combine high gain, wide bandwidths, high-current drivability, and structural simplicity.

Electron lifetime measurements of heavily C-doped InGaAs and GaAsSb as a function of the doping density

The electron lifetime has been measured by time-resolved differential transmission experiments in heavily carbon-doped p-type InGaAs and GaAsSb, grown lattice matched on InP by molecular beam epitaxy. It is found inversely proportional to the square of the doping in both alloys, a result typical of Auger recombination dominated processes. It is shown that the electron lifetime is almost twice larger in GaAsSb than in InGaAs for large p-type doping, thus confirming that GaAsSb is a strong contender for the base material of double heterostructure bipolar transistors on InP.

Impact of surface state modeling on the characteristics of InP/GaAsSb/InP DHBTs

We study the effect of non-ideal surface conditions on the characteristics of submicrometer type-II InP/GaAsSb double heterostructure bipolar transistors (DHBTs) by comparing two-dimensional numerical simulations with measured device characteristics. The inclusion of surface effects in simulations enables excellent agreement with measured Gummel characteristics and measured emitter size effects, and shows that recombination at the emitter mesa periphery on the extrinsic base surface is the major source on non-ideality in device characteristics. The simulations also demonstrate that AlInAs emitters should result in weaker surface recombination and emitter size effects.

Improved InP‐based double heterojunction bipolar transistors

This article develops two double heterostructure bipolar transistors (DHBTs) made by low-pressure metamorphic organic chemical vapor deposition (LP-MOCVD). One is a control DHBT with an abrupt base-collector heterojunction (abrupt DHBT) and the other is an improved DHBT with a composite-collector design (composite DHBT). Of the devices with no ledge passivation, the composite DHBT has a high common-emitter current gain, a low offset voltage and voltage-independent collector current characteristics, unlike the abrupt DHBT. The favorable performance of the composite DHBT follows mainly from the optimal collector design, which effectively lowers the potential spike at the base-collector heterojunction. Furthermore, measurements of the composite DHBT with and without n-InP emitter ledges are made. The composite DHBT with emitter ledges has a current gain of 180, which is 44% higher than that of the device with no emitter ledge. The higher current gain is attributable to the lower base surface recombination current in the composite DHBT with a ledge. The effectiveness of the composite-collector design and the emitter ledge process of the presented DHBT is proven. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both fT and fmax. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600 mVpp. The extracted 40 GHz clock signal shows a phase noise as low as -98 dBc/Hz at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of -4.8 V, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies

A compact 43-GHz monolithic differential VCO in 0.5-/spl mu/m InP DHBT technology

A compact monolithic integrated differential voltage controlled oscillator (VCO) using 0.5-μm emitter width InP/InGaAs double-heterostructure bipolar transistors with a total chip size of 0.42 mm × 0.46 mm is realized by using cross-coupled configuration for extremely high frequency satellite communications system applications. The device performance of F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> greater than 320 GHz at a current density of 5 mA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 5-V BVceo allows us to achieve a low phase noise 42.5-GHz fundamental VCO with -0.67-dBm output power. The VCO exhibits the phase noise of -106.8 dBc/Hz at 1-MHz offset and -122.3 dBc/Hz at 10-MHz offset from the carrier frequency.

Surface Recombination Currents in “Type-II” NpN InP–GaAsSb–InP Self-Aligned DHBTs

Surface recombination effects are studied in non-passivated non-self-aligned and self-aligned NpN InP-GaAsSb-InP double heterostructure bipolar transistors (DHBTs) down to submicrometer emitter dimensions, and over current densities ranging from 10 A/cm/sup 2/ to 100 kA/cm/sup 2/. The present study is motivated by the drive to scale InP DHBTs for higher speeds and integration densities. Self-aligned InP-GaAsSb-InP DHBTs are characterized by weak emitter size effects (ESEs), and periphery recombination currents are found to be very nearly identical to published results for InP-GaInAs SHBTs despite the major differences in emitter junction band alignments ("type-II" versus "type-I") and injection mechanisms (thermal versus hot electron injection). The correspondence of measured periphery currents in both systems indicates that ESEs are dominated by a mechanism common to InP-GaAsSb and InP-GaInAs devices: this requirement is fulfilled by the direct electron injection from the InP emitter mesa sidewalls onto the extrinsic base surface. Consideration of band alignments and surface depletion effects at the extrinsic base surface is used to explain the commonality of emitter size effects in InP-GaAsSb and InP-GaInAs devices.

Passivation of InP/GaAsSb/InP double heterostructure bipolar transistors with ultra thin base layer by low-temperature deposited SiN x

The InP/GaAsSb/InP double heterostructure bipolar transistors with 20-nm-thick base layer are passivated by low-temperature deposited SiN x . The SiN x passivation results in an increase of the current gain, seen from common-emitter I– V characteristics. An improvement of the Early voltage is also observed after the passivation. The study of the forward Gummel plots shows that the collector current keeps unchanged, while the base current decreases after SiN x passivation. A decrease of the base current ideality factor is found by the SiN x passivation. The passivation also results in an improvement of the base–collector junction. In contrast, the leakage current of the base–collector junction increases tow orders after passivation.

Extraction of the Average Collector Velocity in High-Speed “Type-II” InP–GaAsSb–InP DHBTs

In "type-II" NpN InP-GaAsSb-InP double heterostructure bipolar transistors DHBTs), the p/sup +/ GaAsSb base conduction band edge lies /spl Delta/E/sub C/ above the InP collector conduction band: a small ballistic injection energy /spl Delta/E/sub C/ is thus imparted to electrons as they are launched into the collector. The resulting high initial velocity should in principle reduce the collector signal delay time in comparison to the case where thermal electrons are accelerated by the collector electric field alone. We extract the bias dependence of the average collector electron velocity in high-speed InP-GaAs/sub 0.62/Sb/sub 0.38/-InP DHBTs, and find a maximum average velocity reaching 4/spl times/10/sup 7/ cm/s across a 2000 /spl Aring/ InP collector. This finding provides evidence of the performance advantage afforded by abrupt type-II base/collector (B/C) junctions for collector transport when compared to other B/C junctions.

Comparison of the passivation effects on self- and non-self-aligned InP/InGaAs/InP double heterostructure bipolar transistors by low-temperature deposited SiNx

Both the self- and non-self-aligned graded-base InP/InGaAs/InP double heterostructure bipolar transistors (DHBTs) were passivated by room-temperature deposited SiNx. Current gains were found to increase significantly after SiNx passivation. The passivation resulted in an increase in the leakage current of base-collector junction. The larger leakage current in the non-self-aligned DHBT made the sudden increase of the collector current in the common-emitter I–V curve occur at smaller collector-emitter bias than that in the self-aligned DHBT, which has smaller leakage current. Further increase in the current gain was found after the DHBTs were exposed to air for 200 days. The leakage current in the base-collector diode was reduced. The sudden increase of the collector current in the non-self-aligned DHBT in the common-emitter I–V characteristics was also suppressed. Investigation of reverse Gummel plots showed that the surface recombination in the base-collector diode was suppressed by the passivation. The leakage current in the base-collector diode was attributed to the increase of the generation rate.

InP-based double-heterostructure phototransistors with 135 GHz optical-gain cutoff frequency

A high-speed layer and process compatible phototransistor based on the authors&apos; InP-based double-heterostructure bipolar transistor technology is presented. By using only the base and a thin base–collector spacer as absorption layer, slow drifting holes in the collector layer are avoided. This results in record optical-gain cutoff frequencies of up to 135 GHz at the expense of intrinsic photodiode responsivity in a top-illuminated configuration.

SiGe differential transimpedance amplifier with 50-GHz bandwidth

InP and SiGe technologies are both attractive for design of circuits operating at 40 GB/s and beyond. In this paper, we describe a fully differential SiGe transimpedance amplifier (TIA) suitable for differential phase-shift keying applications. The TIA exhibits 49 dB-/spl Omega/ transimpedance, greater than 50-GHz bandwidth, and input-referred current noise less than 30 pA//spl radic/Hz. For comparison, we have also developed a similar TIA in an InP double-heterostructure bipolar transistor technology. The InP TIA had 48 dB-/spl Omega/ transimpedance and 49-GHz bandwidth.

Ultrahigh-speed InP/InGaAs DHPTs for OEMMICs

This paper presents an ultrahigh-speed InP/InGaAs double-heterostructure phototransistor (DHPT) with a record optical gain cutoff frequency of 82 GHz. This excellent performance originates from the double-heterostructure's compatibility with high-performance double-heterostructure bipolar transistor (DHBT) and a new self-aligned process. To demonstrate the excellent performance of the DHPT, two kinds of optoelectronic MMICs (OEMMICs) were designed and fabricated. One is a 40-GHz-band DHPT/DHBT photoreceiver that shows the DHPT's ability to be simultaneously integrated with a high-performance DHBT. The 40 GHz operation frequency is also the highest reported for monolithically integrated HPT/HBT photoreceivers. The other is a direct optical injection-locked oscillator that can extract an electrical clock signal from optical data streams. The OEMMICs are promising for compact and low-power-consumption optical receivers on an InP platform for millimeter-wave photonics and ultrahigh-speed optical communication systems.