Double-gate Thin-film Transistors Research Articles

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

Double-gate thin film transistor with suspended-gate applicable to tactile force sensor

This paper presents a straightforward, low-cost, and effective integration process for the fabrication of membrane gate thin film transistors (TFTs) with an air gap. The membrane gate TFT with an air gap can be used as the highly sensitive tactile force sensor. The suspended membrane gate with an air gap as the insulator layer is formed by multiple photolithography steps and photoresist sacrificial layers. The viscosity of the photoresist and the spin speed was used to modify the thickness of the air gap during the coating process. The tactile force was measured by monitoring the drain current of the TFT as the force changed the thickness of the air gap. The sensitivity of the devices was enhanced by an optimal gate size and low Young’s modulus of the gate material. This simple process has the potential for the production of small, versatile, and highly sensitive sensors.

Semiconducting single-walled carbon nanotube network-based double-gate thin-film transistors for high-performance aqueous chemical sensor applications

In this study, we fabricated a highly sensitive separative extended gate chemically modified field effect transistor (SEG-ChemFET) sensor using a semiconducting single-walled carbon nanotube (scSWCNT) network. To improve the stability and sensitivity of the scSWNT channel layer, we fabricated a double-gate structure FET transducer with a passivated channel using top- and bottom-gate insulators and applied a separate sensing membrane. The scSWCNT network channel was formed by solution process. In order to increase the sensitivity, a low-k spin-on-glass (SOG) film and a stacked Ta2O5/SiO2 film were formed as top-gate and engineered bottom-gate insulators, respectively, which improved the coupling ratio. As a result, the fabricated scSWCNT ChemFET sensor exhibited sensitivity of 365.65 mV/pH sensitivity, which is much higher than the Nernst limit (59.5 mV/pH), a linearity of 99.88%, and a drift rate of 72.44 mV/h. Thus, we expect this research to have important applications for high-sensitivity biosensors.

(Invited) Illumination Light Wavelength Effects on Double-Gate a-IGZO Thin Film Transistor with Top-Gate-to-Source/Drain Offset Structure

Recently, oxide-based thin-film transistors (TFTs) have attracted considerable attention for use in next-generation flat panel displays due to high mobility (µ eff), large-area uniformity, and large band gap semiconductor material [1,2]. Amorphous IGZO (a-IGZO) is widely accepted as a promising channel material for TFT applications [3]. Many researchers reported that the wavelength of the illumination light affected characteristics of a-IGZO TFTs [4,5]. Recently, it was observed that characteristics of the a-IGZO TFT change under light illumination and at the raised temperature [4]. The sub-threshold swing (S) increased and the threshold voltage (V th) shifted to the negative direction when the wavelength was decreased [5]. However, the influence of the light wavelength on top- and double-gate of a-IGZO TFTs have not been clarified in detail. In this study, characteristics of top- and double-gate a-IGZO TFTs illuminated with lights of different wavelengths are reported. Bottom-gate a-IGZO TFTs with an inverted staggered structure were fabricated on a glass substrate. First, a 150 nm-thick molybdenum (Mo) film was used as the gate electrode material. Then, a gate insulator of SiOx (300 nm) was deposited using the plasma-enhanced chemical vapor deposition (PE-CVD) method. A 50 nm-thick a-IGZO layer was then sputter deposited from an In2O3: Ga2O3:ZnO (1:1:1 mole ratio) target at room temperature. Next, a SiOx (200 nm)/AlOx (20 nm) stack was deposited as the etch stopper layer. The Ti/Al/Ti source and drain electrodes were deposited in contact with the a-IGZO layer through via holes in the etch stop layer. After the device was passivated with a PECVD SiOx (100 nm)/SiNx (100 nm) stack, an ITO film was deposited and etched into the top gate electrode. The top electrode is located at the center position of the bottom-gate electrode with a gap space of 20 μm from each of the source and drain electrodes. The channel length (L) and width (W) of the bottom-gate were 80 and 50 μm, respectively. All electrical measurements were carried out in ambient air using an Agilent 4155C precision semiconductor parameter analyzer. During the illumination measurement, the TFT was illuminated with a LED light from the top electrode direction. The wavelengths are: 630 nm (red), 560 nm (green), 470 nm (blue) and 395 nm (UV. The light intensity was 0.3 mW cm−2. Figures 1 and 2 show the transfer characteristics of the a-IGZO TFTs measured at room temperature in dark and under red, green, blue, and UV illuminations separately. The µ eff was extracted from the transconductance in the saturation region. The Vth was the gate voltage (V GS) at the drain current (I DS) of 1 nA. The S was the required VGS when I DS changed from 1 to 10 nA. Electrical properties of top- and double-gate TFTs are summarized in Tables 1 and 2. Those parameters were estimated from transfer characteristics at V DS= 20 V. With the decrease of the wavelength, the top-gate TFT’s mobility is increased but both V th and S deteriorate. For the double-gate TFT, similar but less obvious tends are observed except for the Vth . When the wavelength changed from 2 eV (red) to 3.19 eV (UV), much more charge carries are generated in the a-IGZO layer, which induced higher conductivity in the channel. Therefore, µ eff, Vth and S in both top- and double-gate IGZO TFTs are changed. Jingxin Jiang would like to thank the Doctoral Scientific Research Foundation of Liaoning Province, No. 201601156 and China Scholarship Council for proving financial support for her visit to Thin Film Nano and Microelectronics Laboratory, Texas A&M University through the Postdoctoral Research Program. [1] T. Kamiya, K. Nomura, and H. Hosono, Sci. Technol. Adv. Mater. 11, 044305 (2010). [2] J. Jiang, D. Wang, T. Matsuda, M. Kimura, S. Liu and M. Furuta, J. Nano R., 46, 93 (2017). [3] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature 432, 488 (2004). [4] T.-C. Chen, Y. Kuo, T.-C. Chang, M.-C. Chen and H.-M. Chen, J. Phys. D: Appl. Phys. 50, 42LT02 (2017). [5] X. Huang, C. Wu, H. Lu, F. Ren, Q. Xu, H. Ou, R. Zhang, and Y. Zheng, Appl. Phys. Lett., 100, 243505 (2012). Figure 1

(Invited) Illumination Light Wavelength Effects on Double-Gate a-IGZO Thin Film Transistor with Top-Gate-to-Source/Drain Offset Structure

Electrical properties of the double-gate amorphous In-Ga-Zn-O thin film transistor with the top-gate-to-source/drain offset structure were investigated in dark and under visible and UV light illumination conditions. With the increase of the band gap energy of the incident light, the amount of charge carries generated in the semiconductor channel layer was increased, which enhanced the field effect mobility and increased the leakage current. At the same time, defects were created, which deteriorated the threshold voltage and subthreshold slope. For the top-gate thin film transistor, the UV illumination seriously deteriorated all device characteristics except the leakage current because of the reduction of oxygen vacancies. The performance of the double-gate thin film transistor was dominated by the bottom-gate transistor. Light illumination effects in the bottom- and double-gate transistors were similar but much less serious than those of the top-gate transistor. The understanding of the wavelength-dependent light illumination effect is critical to double-gate thin film transistor applications.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing the Low-Temperature Polycrystalline-Si (LTPS) as their active areas are very crucial for the system-on-glass (SOG). The liquid-crystal display (LCD) or organic light emitting diode display are fabricated in the display area and their controls are performed by the micro-computer that is formed in the peripheral area. The application of high-performance poly-Si TFTs to the high-definition LCD light valves for projectors was reported for the first time[1]. Therefore, the requirements for the recrystallized Si film are a high quality, a large grain formation and a position control of the nucleation. To satisfy those requirements, a super lateral growth (SLG)[2] using the excimer laser annealing (ELA), a phase-modulated ELA[3], a solid-phase crystallization followed by ELA[1], a low-temperature solid-phase excimer laser crystallization[4], a Pd:YAG laser crystallization[5], a soft X-ray crystallization (SXC)[6] have been studied. For the device structure, the double gate TFT[7] and the tunnel TFT[8] have been developed. In our group, the low-temperature crystallization methods and the novel TFT utilizing tunnel effect have been researched. Low-temperature crystallization: For the ELA method, the mechanism of multi-pulse ELA crystallization has been clarified and a large grained film with a high-quality[4] was provided. In addition, hydrogens in a-Si film greatly influenced the crystallinity and grain size of the poly-Si[9,10] and we discovered the advantage in ELA of hydrogen–modulation-doped a-Silicon Layer[11]. For the SXC, a low-temperature crystallization of a-Si, Ge and SixGe1-x film was researched and developed using the short undulator as a light source. The fundamental process of the SXC-method is a local excitation of core electrons to vacuum level by photons followed by the atom movement due to the Coulomb repulsion, which results in the lower temperature process. The SXC-method reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x film by 100 - 150 degree C as compared with the conv. thermal crystallization. Novel TFT: Although the high-performance TFT with the high carrier mobility and low leakage current utilizing the large single crystalline grains has been intensively researched, it does not successfully operates from the productive viewpoint[12]. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated in a bottom-gate structure. Using a 1.7-nm-thick SiNx film, it reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect as shown in Fig.1[13]. It is considered that the fixed charge in the SiNx film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion. We conclude that TDTFT will suitable as a candidate of the next generation TFT structure.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Real‐time current‐sensing feedback system for compensating process–voltage–temperature variations of display using double‐gate oxide TFT

The shift register of display panel employing double-gate oxide thin-film transistors (TFTs) to compensate the severe degradation of the threshold voltage (V TH) is proposed. In double-gate TFTs, V TH is controlled by adjusting top-gate bias, so that V TH degradation can be stabilised by top-gate bias control. However, an optimum top-gate voltage varies from product to product due to process–voltage–temperature variation. To overcome this variation, a feedback system is designed and fabricated in a 0.18 μm BCDMOS process. The system consists of the shift register current sensing and the searching algorithm for finding optimal top-gate bias of double-gate TFTs. It is verified that proposed system successfully stabilised the operation of the shift register up to 80°C.

Real-Time External Compensation of Threshold Voltage Shift Using Double-Gate Oxide TFTs in a Gate Driving System

In order to suppress the malfunction caused by the shift of the threshold voltage (VTH) of oxide thin film transistors (TFTs) to a negative value, double-gate TFTs are used in the shift register of the gate driving system to control VTH by adjusting the top gate bias. The proposed circuit detects the current consumption of the shift register and adjusts VTH so that the current consumption of the shift register is regulated within the desired value. The system includes a compensation algorithm, which can search for an optimized top gate bias in various circumstances such as process fluctuations and ambient temperature change. The proposed system provides a stable operation compared with a conventional structure especially at high temperature. Experimental results show that, in the conventional system without compensation, the output voltage of the shift register deteriorates at $80\, {}^{\circ} {\rm C}$ and above, and the power consumption increases from 1.15 to 2.14 mW after 21600 s of continuous operation at $60\, {}^{\circ} {\rm C}$ . On the other hand, the proposed system provides a stable gate output up to $100\, {}^{\circ} {\rm C}$ and keeps the power consumption below 1.10 mW by adjusting the top gate bias responding to environment changes.

Low-Power Double-Gate ZnO TFT Active Rectifier

This letter reports a low-power full-wave active rectifier using double-gate ZnO thin-film transistors (TFTs). The active rectifier is designed to operate at low voltage and low power to allow integration with mechanical energy harvesters. Double-gate TFTs allow the TFT threshold voltage to be tuned and enable enhancement/depletion-mode circuits with high gain and low power consumption. The active rectifier is designed to work with input voltage as small as 200-mV peak-to-peak and frequencies up to 4 Hz. The active rectifier circuit includes 12 TFTs and operates with a power consumption <150 nW. The low fabrication temperature for the active rectifier circuit allows direct and distributed integration with micro-electromechanical energy harvesters.

Flexible Self-Aligned Double-Gate IGZO TFT

In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> and fabricated on free standing plastic foil, using self-alignment (SA) are presented. The usage of transparent indium-tin-oxide instead of opaque metals enables SA of source-, drain-, and top-gate contacts. Hence, all layers, which can cause parasitic capacitances, are structured by SA. Compared with bottom-gate reference TFTs fabricated on the same substrate, DG TFTs exhibit a by 68% increased transconductance and a subthreshold swing as low as 109 mV/dec decade (-37%). The clockwise hysteresis of the DG TFTs is as small as 5 mV. Because of SA, the source/drain to gate overlaps are as small as ≈ 1 μm leading to parasitic overlap capacitances of 5.5 fF μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . Therefore a transit frequency of 5.6 MHz is measured on 7.5 μm long transistors. In addition, the flexible devices stay fully operational when bent to a tensile radius of 6 mm.

Short Channel Effects on LTPS TFT Degradation

Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for future large area electronics, due to their capability to electrically control TFT characteristics. The scope of this paper is to study how high performance DG polysilicon TFT degradation is affected by shrinking of the channel length. We applied equivalent dc stress in DG TFTs of different top gate length ${L}_{\rm top}$ , with channel width ${W} = 8 \mu$ m and bottom gate length fixed at ${L}_{\rm bot} = 4 \mu$ m. Also, to ensure that we only see effects from the top gate operation, the bottom gate bias was kept constant at ${-}$ 3 V, pushing the carriers towards the top interface. Degradation seemed to be much more intense in the longer device, despite the scaling of the stress field. This could be attributed to the larger number of sub-boundaries and grain boundaries as ${L}_{\rm top}$ increases, causing larger scattering of the carriers towards the top interface and larger grain-boundary state creation. Low frequency noise measurements support the conclusions regarding the proposed degradation mechanisms of DG polysilicon TFTs with shrinking channel length.

Low-Voltage Double-Gate ZnO Thin-Film Transistor Circuits

In this letter, we report double-gate ZnO thin-film transistor (TFT) circuits deposited by plasma-enhanced atomic layer deposition that are suitable for low-voltage operation. Compared to bottom-gate-only ZnO TFTs, double-gate ZnO TFTs have improved mobility, subthreshold slope, and bias stability. In this letter, the TFT top gate is used to adjust the bottom-gate turn-on and threshold voltage. This allows the logic transition point for circuits to be adjusted for operation at a low voltage. Using this approach, high-gain inverters (gain >100) and low-voltage ring oscillators using double-gate TFTs have been demonstrated. Double-gate inverters with a beta ratio of 5 have a gain larger than 100. Fifteen-stage double-gate ZnO TFT ring oscillators operate with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.5 V, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 28 μA, and propagation delay of 2 μs per stage.

Flexible double gate a-IGZO TFT fabricated on free standing polyimide foil

In this paper, the concept of double gate transistors is applied to mechanically flexible amorphous indium–gallium–zinc-oxide (a-IGZO) thin film transistors (TFTs) fabricated on free standing plastic foil. Due to the temperature sensitivity of the plastic substrate, a-IGZO is a suitable semiconductor because it provides carrier mobilities around 10cm2/Vs when deposited at room temperature. Double gate TFTs with connected bottom and top gate are compared to bottom gate reference TFTs fabricated on the same substrate. Double gate a-IGZO TFTs exhibit a by 78% increased gate capacitance, a by 700mV higher threshold voltage, and therefore an up to 92% increased transconductance when characterized at the same gate voltage above threshold (over-bias voltage). The subthreshold swing and the on/off current ratios are improved as well, and reach excellent values of 69mV/dec and 2×109, respectively. The mechanical flexibility of double gate TFTs compared to bottom gate TTFs is investigated, and device operation is shown while the double gate TFT is exposed to tensile strain of 0.55%, induced by bending to a radius of 5mm.

Tuning the Threshold Voltage of Double-Gate Low-Voltage Transparent Oxide-Based TFTs by a Lateral In-Plane Gate

Double-gate low-voltage transparent oxide-based thin-film transistors (TFTs) with a lateral in-plane gate are self aligned by only one metal shadow mask. The threshold voltage of such devices can be tuned in a wide range from -1.07 to 0.78 V by the lateral in-plane gate, which allows the device switching from a depletion to an enhancement-mode operation. High performance with a field-effect mobility of >; 10 cm2/V · s, a current on/off ratio of ~3 × 105, and a low subthreshold swing of ~195 mV/decade is obtained at various voltage biases of the in-plane gate. Such double-gate TFTs are promising for next-generation transparent electronics with low power consumption.

High Performance and Stability of Double-Gate Hf–In–Zn–O Thin-Film Transistors Under Illumination

Hafnium indium zinc oxide thin-film transistors (TFTs) with a double-gate structure were evaluated for the first time. Compared with devices with a single bottom gate, TFTs with an additional top gate exhibit improved subthreshold swing, threshold voltage, and field-effect mobility, as well as smaller subthreshold currents upon exposure to visible light. This phenomenon is attributed to the more effective suppression of excess photocurrents by the application of a double-gate structure. Negative-bias stress experiments under illumination indicate that the double-gate TFT exhibits very high stability compared with the device with a single-gate configuration.

Highly Stable Double-Gate Ga–In–Zn–O Thin-Film Transistor

We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> ) shift of the DG TFT after 3 h of positive-bias temperature stress ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = + 20 V, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = + 0.1 V, and Temperature = 60°C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = - 20 V, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = + 10 V, and Temperature = 60°C] are more dramatic: The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is -9.1 V. With backlight illumination, the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> shift of the SG TFT under the same NBTS becomes severe ( -11.1 V). However, it remains as small as -0.7 V for the DG TFT.

High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization

In this work, high-performance low-temperature poly-silicon (LTPS) thin film transistors (TFTs) with double-gate (DG) structure and lateral grain growth have been demonstrated by excimer laser crystallization (ELC). Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current–voltage characteristics as compared with the conventional solid-phase crystallized (SPC) poly-Si double-gate TFTs or conventional ELC top-gate (TG) TFTs. The proposed ELC DG TFTs ( W/ L = 1.5/1.5 μm) had the field-effect-mobility exceeding 400 cm 2/V s, on/off current ratio higher than 10 8, superior short-channel characteristics and higher current drivability.

High-Performance Short-Channel Double-Gate Low-Temperature Polysilicon Thin-Film Transistors Using Excimer Laser Crystallization

In this letter, high-performance low-temperature polysilicon thin-film transistors (TFTs) with double-gate (DG) structure and controlled lateral grain growth have been demonstrated by excimer laser crystallization. Via a proper excimer laser condition, along with the a-Si step height beside the bottom gate, a superlateral growth of Si was formed in the channel length plateau. Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current-voltage characteristics, as compared with the conventional top-gate ones. The proposed DG TFTs ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = 1/1 mum) had the field-effect mobility exceeding 550 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots, an on/off current ratio that is higher than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> , superior short-channel characteristics, and higher current drivability. In addition, the device-to-device uniformity could be improved since grain growth could be artificially controlled by the spatial plateau structure.

Front and Back Channel Properties of Asymmetrical Double-Gate Polysilicon TFTs

Polycrystalline silicon thin-film transistors (TFTs) with different front- and back-gate lengths are investigated. In addition, the laser annealing process yields high-quality directional grains that enable us to orient TFT channels parallel or perpendicular to the grain boundaries. It is demonstrated that the turn-on voltage is not dependent on grain orientation, unlike the subthreshold swing and the maximum transconductance. Moreover, it is shown that double-gate TFTs are fully depleted and therefore back interface properties exert critical influence on the overall TFT electrical performance. From electrical measurements the back interface state density was estimated to reach values and it was shown that the electrical performance of the double-gate devices is highly dependent on the back-to-front gate-length ratio.