Double Gate Junctionless Transistor Research Articles

Trench Dual Gate Junctionless Field Effect Transistor

Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.

Influence of deep level trap charges on the reliability of asymmetric doped double gate JunctionLess transistor (AD-DG-JLT)

A study based on the numerical simulation of Double Gate JunctionLess Transistor DG-JLT has been presented under the influence of Trap Charges (TC) inside the oxide or at the oxide/channel interface using ATLAS TCAD software. These trap charges may be generated due to various effects like aging and exposure to radiation and chemical environment etc. and thus leading to variability in the device behavior. To evaluate the impact of TC, the forward and reverse threshold voltage were calculated by altering the gate voltage from zero to positive and subsequently returning to zero, while employing various gate bias durations. Asymmetric doping has also been employed to study the variability in DG-JLT with TC as compared to Uniformly Doped DG-JLT (UD-DG-JLT). Furthermore, the investigation is expanded to evaluate how the performance of AD-DG-JLT is affected by the Dual Material Gate (DMG) in the presence of generated TC. To explore the robustness of the device, breakdown voltage (BV) has been examined with varying TC and device specifications. The impact of the trap energy level (EC-ET) on the BV of the devices has also been explored. Extensive numerical simulations have also been performed to showcase the results regarding the change in drain current caused by Single Event Upset (SEU).

Performance optimization of electrically variable double gate junctionless transistor with HfO2 gate dielectric

Performance optimization of electrically variable double gate junctionless transistor with HfO2 gate dielectric

Simulation of Junctionless Transistor for Low Power Mix Circuit

Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction transistor.

Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet

In this paper, after calibrating the models and parameters used in the simulations based on experimental data, by using the opposite doping in the channel and between the gates in an asymmetric double-gate junctionless (JL) transistor with the 3nm gate length, a charge sheet (CS) was created. The results showed that, due to creating CS in the middle of the channel, the horizontal electric field was increased, thus more major carriers were depleted from the middle of the channel. With the analysis of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ DS}} - \text{V}_{\mathrm{ GS}}$ </tex-math></inline-formula> diagrams at different temperatures, it was concluded that in the CS JL MOSFET, while the ON-state current is very close to compared that in the JL MOSFET (same structure without CS), the drain leakage current has decreased by around 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . Furthermore, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ DS}} - \text{V}_{\mathrm{ DS}}$ </tex-math></inline-formula> diagram showed that the drain current in the CS JL MOSFET was much less affected by the drain voltage compared to that in the JL MOSFET. Also in AC analysis and at 1MHz frequency, by using CS the parasitic capacitances were reduced. Due to the improvement obtained in the presence of the charge sheet, the proposed structure was used in designing an inverter. The results showed that in the presence of the charge sheet, logical high input range, and logical low input range were increased, and also, noise margin low (NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ) and noise margin high (NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> ) were improved.

Enhanced Performance Double-gate Junction-less Tunnel Field Effect Transistor for Bio-Sensing Application

In this work, a double gate junction-less tunnel FET (DG-JLTFET) has been evaluated for biosensing applications. Tunnelling is the concept in JLTFET which is a heavily doped JL transistor, by decreasing the barrier length between the source and channel of the device which is easily used for switching (ON and OFF) purpose. Based on the research and simulation so far on JLTFET, this has achieved a greater performance when compared to that of MOSFET. JLTFET with more dielectric (k) and low K spacers will give an ON current (0.1 mA/µm) for gate voltage 3V and for off current of (10−15 A/ µm) and performance with Ion/Ioff ratio at 1012 and subthreshold swing with 60 mV/dec is obtained at 20 nm length of the gate at room temperature. So, JLTFET is a better device for switching performance. The evaluation of device performance is also done based on different cavity thicknesses and different dielectric constants. Including these parameters, double gate-pocket-junction-less TFET is highly used in biosensor applications. In the following, we demonstrate high performance based on pocket region which is introduced to implement in JLTFET for biosensor label-free detection

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device’s response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm channel length have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

Effects of Hafnium Oxide on Short Channel Effects and DC Analysis for Double Gate Junctionless Transistors

Effects of Hafnium Oxide on Short Channel Effects and DC Analysis for Double Gate Junctionless Transistors

Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor

Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor

Correlation of Core Thickness and Core Doping with Gate & Spacer Dielectric in Rectangular Core Shell Double Gate Junctionless Transistor

The impression of gate dielectric and spacer dielectric on the performance of rectangular core shell double gate junctionless transistor (RCS-DGJLT) using extensive simulations is studied. The RCS-DGJLT brings captivating response in terms of the performance of the device. The effect of gate dielectric and spacer dielectric is studied for the first time in RCS-DGJLT. The performance of the device gets improve on increasing the dielectric constant till core thickness (t core) = 3 nm for shell thickness (t shell) = 4 nm. However, beyond core thickness 3 nm, the performance degrades much for high k dielectric. Further, the performance is enhanced for t core > 3 nm and higher k dielectric on reducing the core doping. The device performance is also studied by incorporating the spacers. It has been shown that the device performance is best at t core = 4 nm with low k gate dielectric however, the device performance degrades when high k spacer dielectric is used on the same device which is an interesting and different outcome as compared to conventional DGJLT. The ON current and ON/OFF current ratio are improved by ∼3 orders of magnitude using highly doped source/drain region(HD-S/D) with high k spacers. The results show that the core is the integral part of the device, any engineering like spacers, gate dielectrics applied to RCS-DGJLT requires the optimization of the core carefully for better device performance.

Ultra-low-power subthreshold logic with germanium junctionless transistors

The present work investigates the suitability of Ge junctionless (JL) transistors for subthreshold logic applications. Considering that Ge exhibits a higher degree of short channel effects due to its higher permittivity, a semi-analytical model is first developed to capture the potential distribution and electron concentration in double gate (DG) Ge JL transistors with underlap regions for subthreshold operation. The model accurately predicts threshold voltage, drain-induced barrier lowering and subthreshold swing in Ge-based DG JL transistors. The work is extended to evaluate the subthreshold drain current for n-type and p-type DG Ge JL devices and the approach is adapted to extract three key technology-dependent parameters for ultra-low-power (ULP) (subthreshold) operation. The technology-dependent parameters are then utilized to evaluate key performance metrics of a subthreshold inverter. The upper and lower output voltage swing values, logic threshold voltage, and gain of the subthreshold inverter agree reasonably well with the developed modeling framework. The impact of technology downscaling, from a 5 nm to 0.7 nm node, on the performance of DG Ge JL subthreshold inverter is investigated, and possible options to enhance gain are outlined. Transient analysis highlighting NOT, NAND and NOR logic functionality with subthreshold Ge JL transistors has been investigated. Apart from base device and circuit assessment, the work also investigates the sensitivity of key metrics on physical transistor dimensions, supply voltage and temperature. The work showcases the potential benefits of optimally designed ULP n-type and p-type metal–oxide–semiconductor Ge JL devices for subthreshold logic applications.

TCAD-Based Investigation of Double Gate JunctionLess Transistor for UV Photodetector

In this work, TCAD-based investigation of junctionLess (JL) architecture having double gate (DG) has been performed for visualizing the sensitivity of the device against light intensity. Comparison has been drawn between conventional DG MOSFET and DG-JL transistor (DG-JLT) under dark and light conditions. Effect of light intensity and wavelength has been modulated to optimize the device sensitivity. Higher shift in the drain current (in subthreshold region) has been observed at 0.35 μm of wavelength, i.e., more sensitive to ultraviolet (UV) light. The improved sensitivity of DG-JLT as compared to DG-MOSFET is due to the better subthreshold characteristics of the device (i.e., lower leakage current and subthreshold slope). From the results, it can be concluded that the DG-JLT with channel doping of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , 10 nm of channel thickness, and having 1 nm of oxide thickness is the best possible choice for UV photodetector due to high sensitivity and responsivity. It has also been observed that more optimizing parameters are available with DG-JLT as the DG-MOSFET is immune toward the device parameter variation.

Impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor: A Numerical Investigation

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ V gs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ V gs = −1 V for L S = L D = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ V gs = 0 V) and tunneling current (2 × 10−8 A @ V gs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ V gs = −1 V), moderate lattice temperature (326) and better I on/I off ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect.

Investigation of Gate Material Engineering in Junctionless Transistor for Digital and Analog Applications

In this paper, we propose dual material gate with dual-k dielectric gate oxide double gate junctionless transistor ‘DMG-DK-JLT’ for significant enhancement of performance. We showed, using 2D simulation that the proposed DMG-DK-JLT exhibit: 1) suppressed gate induced drain leakage due to band to band tunneling in OFF state (VDS = 1 V, VGS = 0 V) by 5 orders. 2) Impressively high ION/IOFF ratio of ~108. 3) For VGS=VDS = 1 V, DMG-DK-JLT performs better over conventional double gate JLT on various digital and analog performance metrics such as transconductance (Gm, 64% improvement), early voltage (VEA, 107% improvement), intrinsic gain (GmRO, 294% improvement), unity gain cutoff frequency (fT, 48% improvement), output resistance (Ro, 139% improvement), and transconductance-to-drain current ratio (Gm/ID, 218% improvement at VGS = 0.2 V, VDS = 1 V). We also compared its performance on above metrics with other gate material engineered Junctionless transistors. Moreover, we also show these values are further improved several orders by adding high-k gate sidewall spacer to our proposed DMG-DK-JLT.

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N+ pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N+ SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N+ pocket structure was higher than that of the N+ SiGe pocket, but at high drain voltages, the order was reversed.

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.

Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

The paper presents the investigation of linearity distortion analysis of double gate junctionless transistor with high-k gate dielectrics and gate metals. As double gate junctionless transistors have shown high performance in digital circuits, linearity analysis is carried out to understand nonlinear behavior of the device for RFIC applications. In order to ensure minimum intermodulation and higher order harmonics at the system output, different linearity parameters like Second Order Voltage Intercept Point, Third Order distortion, Third Order Input Intercept Point and Third Order Intermodulation Distortion are evaluated. The results show that junctionless transistor should be biased at appropriate low voltage to ensure better linearity which is desired for RFICs. The effects of high-k gate dielectrics and gate metals on linearity characteristics of junctionless transistor are also investigated. Deterioration of the linearity is observed in junctionless transistor for the use of high-k insulators as gate dielectrics. It is also observed that low work function gate material is suitable to achieve higher linearity in low power applications.

Doping engineering to enhance the performance of a rectangular core shell double gate junctionless field effect transistor

This paper describes different architectures of a rectangular core shell double gate junctionless field effect transistor (RCS-DGJLT). The device performance has been studied when the core has either the same or opposite type of doping to the shell. It is found that an RCS-DGJLT with an oppositely doped core without heavily doped source/drain (S/D) extension regions exhibits an OFF current of ~10−14A and an ON current of ~10−5A. In addition, an RCS-DGJLT with heavily doped S/D extension and different placements of dopant concentration in the shell and core region is explored, so that control of charge carriers in the device during the ON and OFF states can be achieved. Further, the ON current is enhanced by doping engineering in the shell and core region without significantly degrading the OFF current. The RCS-DGJLT with heavily doped S/D extension along with oppositely doped core exhibits an OFF current of ~10−12A and an ON current of ~10−4A. The performance parameters such as the OFF current, ON current, ON/OFF current ratio, subthreshold slope, threshold voltage and transconductance are calculated. The performance of the proposed RCS-DGJLT fused with doping engineering is compared with previously published results on a DGJLT integrated with technology boosters from the literature, and is found to have superior performance to its counterparts.

Investigation on junctionless floating body DRAMs including Trap Assisted Tunneling

Junctionless Transistors (JL) and One-Transistor (1T) DRAMs are concepts that come out in order to improve the scalability of logic and volatile memories, respectively. In some recent papers, Floating Body (FB) DRAMs (a class of 1T-DRAM) and JL transistors have been joined in order to propose a solution to overcome the scaling limit of the conventional 1T-1C DRAM cells. In this paper they are discussed in detail the physics of operation and the performances of FB-DRAM cells based on JL transistors including the effect of Trap-Assisted-Tunneling (TAT), neglected in most of previous works. As expected, TAT severely limits the retention time due to the large doping, in particular during HOLD operation. The discussion is supported by 2D device simulation on a double gate junctionless transistor including the effect of statistical variability induced by random dopant fluctuations, and the technology (bandgap, lifetime) scaling. It is found that the cell, at least at the nanoscale, can work only by independent gate operation, having maximum performance when the bottom gate works at the limit of the BBT bias region during READ, and that at a gate length as large as 100 nm and fin width of 10 nm the cell can sustain the high doping induced variability to a retention time in the order of 1 ms, while the use of materials with higher bandgap (~1.3 eV) than Silicon can improve the retention time to the order of 10 ms. However several concerns remain on their actual use related to the necessary bias level and to the impact of the actual technologies on the lifetime, which strongly affects TAT degradation.

Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement

In this article, a double-gate (DG) junctionless (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n+-p-n+ as in the conventional structures. The proposed topology achieves an elongated retention time ( ${T}_{\text {ret}}$ ) with larger physical barrier thickness ( ${T}_{\text {oxPB}}$ ) and wider barrier offset length ( ${L}_{\text {BO}}$ ) due to a reduction in band-to-band tunneling (BTBT) (during hold “0”) and recombination (during hold “1”). Maximum retention times of ~2.5 s and ~33 ms have been achieved for channel doping of 1019 cm−3 at 27 °C and 85 °C, respectively, with gate length ( ${L}_{g}$ ) of 100 nm at small drain bias ( ${V}_{\text {DS}}$ ) of 1 V during write “1.” Results demonstrate a better gate length scalability and a retention time of ~4 ms at ${L}_{g}$ of 15 nm with thinner Si channel thickness under the gate ( ${T}_{\text {Si}}$ ) and thicker ${T}_{\text {oxPB}}$ . In addition, the effect of temperature on retention time has been analyzed. With optimized ${T}_{\text {oxPB}}$ at ${L}_{g} = {100}$ nm, the retention time decreases due to thermal generation and recombination from ~2.5 s at 27 °C to ~3 ms at 125 °C.