Double Gate Junctionless Transistor Research Articles

Simplified drain current model for pinch‐off double gate junctionless transistor

A simplified analytical drain current model for the long-channel pinch-off junctionless (JL) double-gate field effect transistor (DGFET) is proposed. The drain current is generally expressed in terms of the mobile charge density and it has been expressed in terms of the pinch-off voltage and the gate capacitance. The proposed model is validated against TCAD simulation results, and is able to predict the behaviour of the JL DGFET for different bias conditions and device dimensions, accurately. The transconductance and the transconductance-to-drain-current ratio are important parameters for analogue circuits, and have been calculated and exhibit good agreement with the TCAD results.

A SILICON GERMANIUM GRADED JUNCTIONLESS TRANSISTOR WITH LOW OFF CURRENT

We propose a Ge / Si graded junctionless transistor (JLT) which helps to reduce the band-to-band tunneling current in off-state for highly doped double gate junctionless transistor (DGJLT). In this paper, we show that there is large band-to-band tunneling (BTBT) current in off-state of silicon-channel and germanium-channel DGJLT, which causes increase in the off-state leakage current by several orders. With the help of band-gap engineering, we found that by using Ge / Si graded channel DGJLT off-state band-to-band tunneling current can be reduced. It is also observed that there is large deviation in the off-state leakage current with variation of drain voltage for Si and Ge body DGJLT, which reduces device stability. It is found that in Ge / Si graded DGJLT variation off-state leakage current with drain voltage is controlled. In Si and Ge , DGJLT electrons from the valence band of the channel tunnel to the conduction band of drain leaves holes which causes increased hole concentration in the channel creating parasitic 'BJT'.

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5×1018 and 1×1019cm−3, as well as for layer thicknesses of 10, 15 and 20nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to Vd=0V.

Double-Gate Junctionless Transistor for Analog Applications

In this paper, analog performance of short channel symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The analog performance parameters, namely drain current (I(D)), transconductance (G(m)), transconductance/drain current ratio (G(m)/I(D)), early voltage (V(EA)), drain output conductance (G(D)), output resistance (R(o)), intrinsic gain (G(m)R(o)), gate to source capacitance (C(GS)), gate to drain capacitance (C(GD)) and unity gain cut-off frequency (f(T)) for the n-type DGJLT are systematically investigated with the help of extensive device simulations and are compared with conventional inversion mode symmetric double-gate transistor (DGMOS) of similar dimensions. DGJLT offers superior transconductance/drain current ratio and intrinsic gain in the subthreshold region than its inversion mode counterpart having same dimensions. However, DGMOS presents higher unity gain cut-off frequency which makes it suitable for high speed applications as compared to a DGJLT transistor.

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I D ), ON-state to OFF-state current ratio (I ON /I OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G m R O ), output conductance (G D ), transconductance/drain current ratio (G m /I D ) and unity gain cut-off frequency (f T ). The effects of varying the spacer dielectric constant (k sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.

A Compact Model of Quantum Electron Density at the Subthreshold Region for Double-Gate Junctionless Transistors

A compact model of quantum electron density at the subthreshold region is derived for junctionless (JL) double-gate (DG) FETs. The proposed quantum model is obtained under two different quantum confinement conditions. One is for a case of a thick channel and a heavily doped channel, where quantum confinement effects (QCEs) are modeled by a 1-D quantum harmonic oscillator. The other is for a case of a thin channel, where QCEs are modeled by the use of a 1-D quantum well surrounded by high potential barriers and an energy correction term coming from the depletion charge. It is shown that, regardless of the channel thickness, the quantum confinement is higher in JL than in inversion-mode (IM) DG FETs. However, for a thin channel, the quantum threshold voltage shift is less severe in JL than in IM DG FETs. The proposed model gives an analytical expression for the threshold voltage shift due to QCEs, which can be used as a quantum correction term for compact modeling.

A Full-Range Drain Current Model for Double-Gate Junctionless Transistors

A drain current model available for full-range operation is derived for long-channel double-gate junctionless transistors. Including dopant and mobile carrier charges, a continuous 1-D charge model is derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions. Based on the continuous charge model, the Pao-Sah integral is analytically carried out to obtain a continuous drain current model. The proposed model is appropriate for compact modeling, because it continuously captures the phenomenon of the bulk conduction mechanism in all regions of device operation, including the subthreshold, linear, and saturation regions. It is shown that the model is in complete agreement with the numerical simulations for crucial device parameters and all operational voltage ranges.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.