Ultra-low-power subthreshold logic with germanium junctionless transistors

Abstract

The present work investigates the suitability of Ge junctionless (JL) transistors for subthreshold logic applications. Considering that Ge exhibits a higher degree of short channel effects due to its higher permittivity, a semi-analytical model is first developed to capture the potential distribution and electron concentration in double gate (DG) Ge JL transistors with underlap regions for subthreshold operation. The model accurately predicts threshold voltage, drain-induced barrier lowering and subthreshold swing in Ge-based DG JL transistors. The work is extended to evaluate the subthreshold drain current for n-type and p-type DG Ge JL devices and the approach is adapted to extract three key technology-dependent parameters for ultra-low-power (ULP) (subthreshold) operation. The technology-dependent parameters are then utilized to evaluate key performance metrics of a subthreshold inverter. The upper and lower output voltage swing values, logic threshold voltage, and gain of the subthreshold inverter agree reasonably well with the developed modeling framework. The impact of technology downscaling, from a 5 nm to 0.7 nm node, on the performance of DG Ge JL subthreshold inverter is investigated, and possible options to enhance gain are outlined. Transient analysis highlighting NOT, NAND and NOR logic functionality with subthreshold Ge JL transistors has been investigated. Apart from base device and circuit assessment, the work also investigates the sensitivity of key metrics on physical transistor dimensions, supply voltage and temperature. The work showcases the potential benefits of optimally designed ULP n-type and p-type metal–oxide–semiconductor Ge JL devices for subthreshold logic applications.