Double Gate Junctionless Field Effect Research Articles

Analysis of biosensing performance of Trench Double Gate Junctionless Field Effect Transistor

Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and  transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of  charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.

An analytical 2-D model of triple metal double gate graded channel junctionless MOSFET with hetero-dielectric gate oxide stack

In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO2 and HfO2 is derived. The model illustrates higher drive current and better performance against hazardous SCEs and HCEs in below 30 nm regime. Parabolic approximation method is used here to construct channel potentials and electric fields by solving 2-D Poisson's equation with applicable boundary conditions. The basic central and surface potentials as well as central and surface electric fields are being illustrated, Threshold voltage, DIBL, sub-threshold swing (SS) and a compact current model have also been deduced. These parameters clearly show the benefits of proposed graded-channel triple-metal double-gate structure with hetero-dielectric gate oxide stack. The device has reliability in low power applications because of its better Ion and Ioff control. Finally, the analytical model is validated with self-consistent numerical calculations to illustrate better performance of among available junctionless devices.

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

Analytical modelling and verification of potential profile of DG JLFET with and without stack oxide

ABSTRACT In this paper, a physically based two-dimensional analytical model of potential profile is proposed for both symmetric and asymmetric p-type-doped Double Gate Junctionless Field Effect Transistors (DG JLFETs). The proposed model keeps its validity in the subthreshold region. In order to establish the model, 2-D Poisson’s equation is solved in the channel region while assuming cubic potential distribution along the channel region. We also propose a 2-D analytical model of symmetric Double Gate Stack-Oxide Junctionless Field Effect Transistors (DGS JLFETs). In order to check out the validity of our proposed model, we have used SILVACO ATLAS simulator. Comparison of potential distribution is made between different structures. Between symmetric and asymmetric structures, symmetric structure shows better potential profile as they have shown higher potential distribution in channel region. But when DG JLFET is compared with DGS JLFET, we find better potential profile distribution in DGS JLFET. Important performance parameters like Ion/Ioff ratio, SS, DIBL, Threshold Voltage, I–V characteristics for different structures are found out and compared among them. Asymmetric structure with same electrode materials in both gates but having lower bottom gate oxide thickness showed better performances like higher Ion/Ioff ratio, lower SS, less DIBL compared to other DG JLFETs with and without stack oxide.

Doping engineering to enhance the performance of a rectangular core shell double gate junctionless field effect transistor

This paper describes different architectures of a rectangular core shell double gate junctionless field effect transistor (RCS-DGJLT). The device performance has been studied when the core has either the same or opposite type of doping to the shell. It is found that an RCS-DGJLT with an oppositely doped core without heavily doped source/drain (S/D) extension regions exhibits an OFF current of ~10−14A and an ON current of ~10−5A. In addition, an RCS-DGJLT with heavily doped S/D extension and different placements of dopant concentration in the shell and core region is explored, so that control of charge carriers in the device during the ON and OFF states can be achieved. Further, the ON current is enhanced by doping engineering in the shell and core region without significantly degrading the OFF current. The RCS-DGJLT with heavily doped S/D extension along with oppositely doped core exhibits an OFF current of ~10−12A and an ON current of ~10−4A. The performance parameters such as the OFF current, ON current, ON/OFF current ratio, subthreshold slope, threshold voltage and transconductance are calculated. The performance of the proposed RCS-DGJLT fused with doping engineering is compared with previously published results on a DGJLT integrated with technology boosters from the literature, and is found to have superior performance to its counterparts.

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

A rectangular core is inserted in double gate junctionless transistor (DGJLT) which separates the top shell and bottom shell in the device called as rectangular core–shell double gate junctionless transistor (RCS-DGJLT). The core doping and core thickness are optimized to improve the performance of RCS-DGJLT. The core thickness is optimized for different shell thicknesses in the device which has not been explored yet in the literature. An interesting observation is found that the core thickness should be equal to the shell thickness for smaller shell thicknesses, whereas the thicker core is required for larger shell thicknesses. RCS-DGJLT has shown remarkable improvement than DGJLT. Further, the effect of gate misalignment on either side (source/drain) of the channel in RCS-DGJLT and DGJLT is studied and compared on the basis of device performance. The study of gate misalignment becomes essential due to the complications on achieving perfectly aligned gates during the fabrication of double gate device. An RCS-DGJLT is found to have better tolerance to gate misalignment than DGJLT. The best parametric values like OFF current is ∼10–16A, ON current is ∼10–5A, subthreshold slope is nearly 66.2 mV/decade, ON/OFF current ratio is ∼1010, drain induced barrier lowering is ∼42.1 mV V−1 and threshold voltage ∼0.56 V at perfectly aligned gate condition is obtained on keeping core and shell thickness at 3 nm each. As per the analysis, the gate misalignment up to 20% on either side of the channel does not impact the performance parameters much and hence reduces the stress of meeting the requirement of perfect gate alignment.

Performance enhancement of core-shell JLFET by gate/dielectric engineering

ABSTRACTIn this paper, enhancement of volume depletion is studied on P-type double gate junctionless Field Effect Transistor (P-DGJLFET) by Gate work function and Gate dielectric engineering. The formation of parasitic BJT action in junctionless device along with DIBL effect is curtailed by integrating Rectangular Core-Shell (RCS) architecture with varying core doping along with different gate oxides and electrodes, respectively. After validating our simulations with the experimental results on Junctionless P-type FET, we demonstrated that RCS based P-DGJLFET with high K dielectric and aluminium as gate electrode exhibits superior ON/OFF ratio, Lower DIBL, better ON current, good OFF current and desired threshold voltage at channel length 5 nm. An exceptional ON/OFF current ratio (ION/IOFF) of 1010 is achieved when core is made thicker than shell. The DIBL is reduced by 62.5% when thin core along with SiO2 is replaced by thick core and HfO2. Also, the stringent requirement of lower work function in Junctionless P-type is relaxed using RCS architecture. The performance of RCS with polysilicon as gate electrode is better than conventional DGJLFET with aluminium as gate electrode. A comprehensive comparison on performances between different technology boosters applied on double gate JLT in the literature and proposed device is also presented.

Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of the silicon body referring to rectangular core–shell (RCS) architecture. The use of RCS has significantly reduced the gate induced drain leakage and therefore, obtaining improved performance parameters. It is observed that the parasitic BJT action gets diminished in RCS architecture due to enlargement of tunneling width at the channel/drain interface. Further, after validating our simulations with the experimental results of junctionless p-type FET we demonstrated that insertion of oppositely doped core in silicon body helps to achieve volume depletion in OFF state. The simulation results show that junctionless FET with RCS architecture exhibit lower OFF current, higher ON/OFF ratio, better drain induced barrier lowering (DIBL) and superior subthreshold slope (SS) at lesser channel lengths. The measured values of OFF current, ON current, ON/OFF ratio, DIBL and SS at channel length 20 nm for RCS architecture are −9.96 × 10−15 A, −2.33 × 10−5 A, 0.23 × 1010, 42.1 mV V−1 and 67.7 mV/decade respectively. Interestingly, we have found a correlation between RCS thickness and channel length. Finally, a complementary metal oxide semiconductor (CMOS) inverter with RCS architecture is also designed. The voltage transfer characteristics of RCS based CMOS has been significantly improved as compared to the conventional junctionless CMOS inverter.

A Surface Potential and Threshold Voltage Model Including Quantum Mechanical Effects for a Dual Material Double Gate Junctionless Field Effect Transistor (DMDG-JLFET)

A Surface Potential and Threshold Voltage Model Including Quantum Mechanical Effects for a Dual Material Double Gate Junctionless Field Effect Transistor (DMDG-JLFET)

Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green’s function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to silicon for potentiometric biosensing.

A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects

In this paper, a unified analytical model for the drain current of a symmetric Double-Gate Junctionless Field-Effect Transistor (DG-JLFET) is presented. The operation of the device has been classified into four modes: subthreshold, semi-depleted, accumulation, and hybrid; with the main focus of this work being on the accumulation mode, which has not been dealt with in detail so far in the literature. A physics-based model, using a simplified one-dimensional approach, has been developed for this mode, and it has been successfully integrated with the model for the hybrid mode. It also includes the effect of carrier mobility degradation due to the transverse electric field, which was hitherto missing in the earlier models reported in the literature. The piece-wise models have been unified using suitable interpolation functions. In addition, the model includes two most important short-channel effects pertaining to DG-JLFETs, namely the Drain Induced Barrier Lowering (DIBL) and the Subthreshold Swing (SS) degradation. The model is completely analytical, and is thus computationally highly efficient. The results of our model have shown an excellent match with those obtained from TCAD simulations for both long- and short-channel devices, as well as with the experimental data reported in the literature.

Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors

This paper reports a 2D analytical model for the subthreshold current and subthreshold swing (SS) of ion-implanted Double-Gate Junctionless Field Effect Transistors (DG-JLFETs) with a vertical Gaussian-like doping profile. The effects of gate length, straggle parameter, oxide thickness, channel thickness, and peak doping concentration on subthreshold current and subthreshold swing have been demonstrated. The model results are validated with the simulation data obtained by 2-D TCAD ATLASTM device simulator. Finally, the performance of a CMOS inverter using the DG-JLFET device has been investigated through ATLASTM TCAD mixed mode circuit simulations.

Physically Based Analytical Modeling of 2D Electrostatic Potential for Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistors in Subthreshold Region

In this paper, we propose an analytical 2D model to calculate the potential in the channel for all types of double gate junctionless field effect transistors (DG JLFETs), which is valid in the subthreshold regime. Model is derived by solving 2D Poisson’s equation along the channel while assuming a cubic potential distribution across the silicon thickness. Threshold voltages of different structures are obtained from the proposed potential model. A comparison of subthreshold behavior i.e. threshold voltage roll-off (TVRO) and drain-induced barrier lowering (DIBL) has been made between symmetric and asymmetric DG JLFETs. The effect of bottom gate flat band voltage of asymmetric structures and bottom gate voltage of dissimilar gate biased structures on the threshold voltage are also investigated.

Physically Based Analytical Modeling of 2D Electrostatic Potential for Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistors in Subthreshold Region

When traditional planar Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are scaled, they lose the gate control over the channel charges because the charges are partially controlled by the drain/source depletion regions [1]. Several types of nonplanar structures with multiple-gated configuration have been proposed for providing better electrostatic control of the charges in the channel region; therefore reducing short-channel effects (SCEs) – like subthreshold slope (SS) degradation, threshold voltage roll-off (TVRO) and drain-induced barrier lowering (DIBL) [2]. However, further miniaturization of such devices becomes quite challenging because of the formation of ultra-shallow and abrupt junctions which requires novel doping and special annealing techniques. Junctionless Field Effect Transistors (JLFETs) have recently been proposed to provide a solution for this issue which typically consist of the source and drain having same doping type as the channel and the thickness of the silicon body thin enough to make the silicon body fully depleted when switched off [3]. Therefore, JLFETs need neither lateral abrupt doping, nor high thermal budget, thus making manufacturing simpler. Besides that JLFETs provide reduced SCEs, an excellent SS, a very low leakage current and high Ion/Ioff ratio compared to conventional MOSFETs [4]. A number of studies based on simulations and analytical solutions have been performed to anticipate the performance of symmetric JLFETs [5-7]. However, a complete analytical treatment for both symmetric and asymmetric double gate JLFETs is necessary to make a comparative study of their performance. In this work, we propose a physically based analytical model of 2D electrostatic potential in the subthreshold region applicable for different structures of JLFET. The schematic cross-sectional view of an n-type double gate JLFET considered in this work is shown in figure 1. The thickness of the source and drain regions are assumed to be zero for the sake of simplicity of modeling. The source and drain electrodes are shown to be present at the two side of the bulk silicon layer which is heavily doped with n-type impurity.  Figure 2 shows the analytical expression of 2D electrostatic potential in the channel region of double gate JLFET. In order to obtain the equation, we analytically solve 2D Poisson’s equation in the channel region using cubic approximation with appropriate boundary conditions. This analytical solution is valid in the subthreshold region of operation for both symmetric and asymmetric double gate JLFETs with similar and dissimilar gate bias configurations. αy and βy in the equation depend on the physical parameters and position along Y-axis which are not shown in the figure. Figure 3 and 4 show the surface plot of 2D channel potential distribution for symmetric and asymmetric double gate n-channel JLFET respectively. In this work we consider symmetric structure with P+ polysilicon as both gate electrodes and asymmetric structure with P+ polysilicon and Ni metal as top and bottom gate electrodes respectively. For a fully depleted double gate JLFETs, the threshold voltage is reached when a portion of the channel is no longer depleted, such that bulk current flows through a neutral path. The threshold voltage of symmetric and asymmetric JLFETs is obtained using the 2D potential model shown in figure 2 by determining the gate voltage for which minimum channel potential along source to drain direction at a particular depth of the silicon channel along the top to bottom gate direction becomes zero. DIBL of JLFETs can be defined as the lowering in the threshold voltage due to the increase in the drain voltage. In this work DIBL is also calculated by varying Vds from 0.1V to 1V. Figure 5 and 6 exhibits the variation of TVRO and DIBL with the channel length of symmetric and asymmetric double gate JLFETs respectively. The asymmetric structure demonstrates smaller TVRO and less DIBL than the symmetric structure when the devices are shrunk into a deep-submicrometer regime. In this work we have obtained a 2D channel potential model in subthreshold region for double gate JLFETs. The analytical potential model is further used to determine TVRO and DIBL of symmetric and asymmetric JLFETS so that performance comparison of subthreshold characteristics can be made between different structures of JLFET. 

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

In this paper, we have developed a pseudo two-dimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect

We investigate the quantum-mechanical effects on the electrical properties of the double-gate junction-less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.

A compact model of subthreshold characteristics for short channel double-gate junctionless field effect transistors

A compact subthreshold characteristics model for short channel fully-depleted double-gate (DG) junctionless field effect transistors (JL FETs) which is based on an approximated solution of 2 dimensional Poisson’s equation has been proposed. The derivation details are introduced and the model’s accuracy has been verified by comparison with both previous models and the TCAD simulations’ results which proves that the subthreshold characteristics such as channel potential distribution, subthrethold drain-to-source current, subthreshold slope, drain-induced-barrier-lowering and threshold voltage can be accurately predicted by our proposed compact model.