Double-gate Carbon Nanotube Field-effect Transistors Research Articles

Impact of thermally -aware environmental conditions on double gate carbon nanotube FET

In this paper, a temperature dependent analytical model of double gate carbon nanotube field effect transistor (DG-CNTFET) has been developed to evaluate the performance of DG-CNTFET under variable thermal environmental conditions. Using the developed model, I–V characteristics of DG-CNTFET have been obtained by nano-TCAD ViDES (nano-Technology Computer Aided Design ViDES) simulator. Further, the effect of temperature on other performance parameters such as output characteristics, ON current, OFF current, subthreshold swing and drain conductance have also been obtained for a temperature ranging from 250 K to 350 K. It has been observed that with increase in temperature, drain current rises which further influence the I–V characteristics of DG-CNTFET. From results, it is revealed that the ON current and drain conductance of DG-CNTFET gets increased with variable temperature. Further, it is also presented in paper that subthreshold swing is also increased under variable thermal environment conditions.

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

<p>The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.</p>

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

<p>The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.</p>

Performance Analysis Of Double-Gate Carbon-Nanotube FET And MOSFET For High Speed Integrated Circuits Design

This paper explains the detailed structure as well as performance of DG-CNTFET (Double Gate Carbon Nanotube Field Effect Transistor) and its performance is compared with the DG-MOSFET (Double Gate Metal Oxide Semiconductor Field Effect Transistor). Various parameters like I-V characteristics, ON current, OFF current and ON to OFF current ratio have been evaluated using nano-TCAD ViDES. Also, the transport description of DG-MOSFET and DG-CNTFET has been described in detail. It has been observed that DG-CNTFET has lower OFF current and higher ON current in comparison to the DG-MOSFET. The higher ON current of DG-CNTFET depicts that it requires less time to turn on the device in comparison with DG-MOSFET. Also, OFF current of the DG-CNTFET is lesser as compared to MOSFET. The DG-CNTFET’s higher ON to OFF current ratio outperforms the DG-MOSFET in term of switching speed of the device. It is proposed that CNTFET can be used as an alternative of MOSFETs for high speed Integrated Circuit (IC) design.

A New Approach to the Characteristics and Short-Channel Effects of Double-Gate Carbon Nanotube Field-Effect Transistors using MATLAB: A Numerical Study

In this paper, first, the impact of different gate arrangements on the short-channel effects of carbon nanotube field-effect transistors with doped source and drain with the self-consistent solution of the three-dimensional Poisson equation and the Schr¨odinger equation with open boundary conditions, within the non-equilibrium Green function, is investigated. The results indicate that the double-gate structure possesses a quasi-ideal subthreshold oscillation and an acceptable decrease in the drain induced barrier even for a relatively thick gate oxide (5 nm). Afterward, the electrical characteristics of the double-gate carbon nanotube field-effect transistors (DG-CNTFET) are investigated. The results demonstrate that an increase in diameter and density of the nanotubes in the DG-CNTFET increases the on-state current. Also, as the drain voltage increases, the off-state current of the DG-CNTFET decreases. In addition, regarding the negative gate voltages, for a high drain voltage, increasing in the drain current due to band-to-band tunnelling requires a larger negative gate voltage, and for a low drain voltage, resonant states appear

FPGA Design with Double-Gate Carbon Nanotube Transistors

Double-gate carbon nanotube field effect transistors (DG-CNTFETs) are novel devices showing an interesting property that consists of controlling the p- or n-type behavior during the device operation. This opens up the opportunity for novel design paradigms. Based on a compact physical model of these devices, we demonstrate the superiority of field-programmable gate arrays (FPGAs) designed with fine-grain DG-CNTFETs compared to FPGAs designed with traditional circuits and with coarse-grain DG-CNTFETs by 13% to 48% respectively in terms of delay.

Modeling and Performance Investigation of the Double-Gate Carbon Nanotube Transistor

In this letter, we propose a semiclassical model for the performance investigation and optimization of the double-gate carbon nanotube field-effect transistor (DG-CNTFET). The DG-CNTFET is effective in controlling the ambipolar conduction that is inherent to Schottky barrier (SB) CNTFETs using two independent gates, namely, the primary gate and the polarity gate. Whereas the primary gate serves to turn the device on and off, the polarity gate can be used to configure the device in either the p-type or the n-type mode of operation. The DG-CNTFET exhibits unipolar conduction and can achieve a large ratio of over six orders of magnitude. Since the proposed model is physics based and does not rely on fitting parameters, it can be used to study the effect of parameters such as CNT chirality, SB height, and gate dielectric thickness on the DG-CNTFET performance.

Molecular electronics and reconfigurable logic

This paper describes a reprogrammable architecture based on regular matrices of fine-grain dynamically reconfigurable cells based on double-gate carbon nanotube field effect transistors (DG-CNTFET) exhibiting ambivalence (p-type or n-type behaviour depending on the back-gate voltage). Using available models, reconfigurable cells have been simulated and performance metrics quantified at 4 GHz operation. A function mapping method suitable for this matrix structure has been devised, and various interconnect topologies have been analysed, showing average mapping success rates to 4 × 4 cell matrices of above 80% for 8-node function graphs. This gives insight into the way data functionality could be coded into the architecture based on such reconfigurable cells for on-the-fly and partial reprogrammability.

CNTFET Modeling and Reconfigurable Logic-Circuit Design

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.

Design of CNTFET-based reconfigurable logic gate

Described is a dynamically reconfigurable 8-function logic gate with seven double-gate carbon nanotube field-effect transistors which demonstrates p-type or n-type behaviour depending on the back-gate voltage. Through simulations, the gate is shown to operate at 20 GHz and has been used to build a 1-bit pipelined full adder using physically identical reconfigurable cells

Design of CNTFET-based reconfigurable logic gate

Described is a dynamically reconfigurable 8-function logic gate with seven double-gate carbon nanotube field-effect transistors which demonstrates p-type or n-type behaviour depending on the back-gate voltage. Through simulations, the gate is shown to operate at 20 GHz and has been used to build a 1-bit pipelined full adder using physically identical reconfigurable cells.