Abstract

This paper describes a reprogrammable architecture based on regular matrices of fine-grain dynamically reconfigurable cells based on double-gate carbon nanotube field effect transistors (DG-CNTFET) exhibiting ambivalence (p-type or n-type behaviour depending on the back-gate voltage). Using available models, reconfigurable cells have been simulated and performance metrics quantified at 4 GHz operation. A function mapping method suitable for this matrix structure has been devised, and various interconnect topologies have been analysed, showing average mapping success rates to 4 × 4 cell matrices of above 80% for 8-node function graphs. This gives insight into the way data functionality could be coded into the architecture based on such reconfigurable cells for on-the-fly and partial reprogrammability.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call