Double Error Detection Research Articles

Implementation of SEC-DED-DAEC Codes using Mentor Graphics

Correction of a single error Double Error Detection (SEC-DED) and Double Adjacent Error Correction (DAEC) are prominent error correction algorithms used in computer memory systems to detect and fix errors that arise during data transfer. In this research, we want to put these ideas into practice and assess how well they work through simulations and experiments. We will research the trade-offs between these strategies' efficiency and reliability and contrast them with other error correction techniques. Our research will involve designing and putting error detection and correction procedures into circuits and algorithms for DAEC and SEC-DED. We will also investigate other methods, including parallel processing and error checking mechanisms, to enhance the performance of these strategies. Our findings may also have applications in other domains where error correction is important, such as communication systems and medical equipment. They will help us understand and enhance error correction techniques used in computer memory systems.

Modified Hamming Codes in Computing Devices Technical Diagnostic Systems

Previously unknown error detection characteristics by types and multiplicities in modified Hamming codes code words are established. The rules for constructing this modification of Hamming codes are described. Detailed characteristic tables of codes with data vectors lengths m = 4...16 are given. The considered code's error detection properties brief analysis is given. The results obtained in the study can be effectively used in the digital computing devices with controllable structures synthesis, as well as in the self-checking concurrent error-detection (CED) circuit synthesis using the Boolean complement method. The modified Hamming codes key property is the impossibility of 100 % double error detection in all code word bits when any single and double errors that occur only in data bits are detected. That is why it is recommended, when synthesizing a CED circuit using the Boolean complement method, to convert only those functions that describe the operating functions of the diagnostic object that will form the modified Hamming code control bits, and to separate the converted and non-convertible outputs into two groups of independent outputs. The experiment results with test combinational circuits presented in the article confirm the effectiveness of their use in the CED circuit synthesis by the Boolean complement method.

On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.

Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review

Abstract: A 40 MHz with 32-bit and 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic read-modify-write operations. The proposed system implements inorder issuing of instructions. The design includes a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating-point execution units, interrupt controller, error control module, and a UART peripheral. Individual interrupts can have up to four levels of primary priority set in the interrupt controller. For the main memory, the error control module provides single error correction and double error detection. For on-chip communication, the Wishbone B.3 bus standard is used. On a Virtex-7 XC7VX485T FFG 1761-2 FPGA-based board, the processor is implemented. The architecture has CoreMark and Dhrystone benchmark ratings of 3.84/MHz and 1.0603 DMIPS/MHz, respectively

Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches

Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC - DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5.67 × 10−4 lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 × 10−3.

Bidirectional wireless power/data transfer via magnetic field

Recently, inductive power transfer (IPT) system has been used for wireless charging of electric vehicles (EVs). However, most of them only treat the issue of single directional wireless power transfer (WPT). This research proposes a novel bi-directional IPT (BD-IPT) scheme EVs, which can simultaneously transmit power/data via magnetic field when the mutual inductance changes. For power transmission, resonant inverters with phase-shift pulse width modulation (PSPWM) are used to generate carrier waves and alternating current. As for data transmission, a dedicated communication method with the accompanied protocol is proposed. Binary phase shift keying (BPSK) is used to simulate the two-quadrature amplitude modulation (QAM), which generates digital signals for data transmission without the need of extra communication links. Hamming codes are combined with single-error correction and double-error detection (SECDED) to ensure communication quality.

MLFTCache: Multilevel Fault Tolerance Scheme for Write-Back L2 Cache Under Irradiation

Cache is prone to soft errors under irradiation, and the incidence rate of multi-bit soft errors in cache memory are becoming larger for modern embedded systems. To improve the cache reliability, we propose a multi-level fault tolerance scheme for write-back L2 cache (MLFTCache). In the workflow of MLFTCache, data bits of cache clean line and dirty line are processed separately. For clean line data bits, 2-way interleaved parity is adopted, and the error is detected and recovered from the next level of memory. For dirty line data bits, the processing is further divided into two layers. The first layer adopts single error correction double error detection (SECDED) code, and the second layer uses multi-bit low redundancy error control with parity sharing (MLREPS) code to detect and correct errors. To reduce the overhead and improve the efficiency of fault tolerance on dirty lines, we adopt two write-back mechanisms. Early write-back mechanism is used to reduce the occurrence of temporal multi-bit soft errors, and emergency write-back mechanism is adopted to deal with the soft error after it is detected. The alpha radiation experiments of Xilinx Zynq-7010 SoC show that cache is prone to multi-bit upsets and the MLFTCache is also dedicated to solving the problem of multi-bit upsets. The cache fault injection and tolerance experiments show that the fault tolerance rate of the MLFTCache proposed in this paper exceeds 90%, while the benchmark schemes are less than 50%. Besides, MLFTCache also has a good performance on dual-core CPU, and its fault tolerance rate on average is 91.34%.

METHODICAL APPARATUS FOR ENSURING THE CORRECTION OF SINGLE ERRORS AND DETECTION OF DOUBLE ERRORS IN STORAGE DEVICES

The analysis of errors that occur during the operation of static storage devices (SD) is carried out. The conclusion is drawn that single and double errors are most likely to occur in memory devices (single errors appear with a probability of up to 80 %, double errors up to 20 – 25 %, and errors of other multiplicity account for up to 2 %). Methods for protecting storage devices from single and double errors are considered. It has been established that at present, for the correction of single errors and the detection of double errors, a modified Hamming code is widely used, which uses for this purpose an additional parity bit for all bits of the code set. The necessity of developing a code that corrects single errors and detects double errors while reducing information redundancy is substantiated. Regularities have been identified that make it possible to form rules for encoding information, and when decoding, to form three additional checks for an error sign to determine erroneous bits in the event of indistinguishable error syndromes. The corrective ability of the proposed method of information coding is investigated. It has been established that the proposed code allows correcting all single errors, detecting all double errors and, at the same time, correcting some of the double errors that simultaneously occur in information and check bits. A regular information coding procedure is described for correcting single and detecting double errors while reducing information redundancy by one check bit and, consequently, reducing hardware costs associated with storing the values of check bits in a memory device. A comparative evaluation of the detection ability and information redundancy of the proposed method with a modified Hamming code is carried out using the example of coding an 11-bit information word. It has been established that for the code (15,11), the implementation of the proposed method makes it possible to detect all single and double errors, correct 100 % of single errors and 27 % of double errors, and use four check digits for these purposes (one less check digit than modified Hamming code). The conclusion is made that the reduction of information redundancy makes it possible to increase the code speed and reduce hardware costs associated with storing the values of a given bit in a memory device and, therefore, increase the probability of failure-free operation and reliability of the memory device operation while reducing information and hardware redundancy.

Correction Masking: A Technique to Implement Efficient SET Tolerant Error Correction Decoders

Single Event Transients (SETs) can be a major concern for combinational circuits. Its importance grows as technology scales because a small charge can create a large disturbance on a circuit node. One example of circuits that can suffer from SETs is the decoders of the Error Correction Codes (ECCs) that are used to protect memories from errors. This paper presents Correction Masking (CM), a technique to implement SET tolerant syndrome decoders. The proposed technique is presented and evaluated both in terms of protection effectiveness and circuit overhead. The results show that it can provide an effective protection while reducing the circuit area and power significantly compared to a Triple Modular Redundancy (TMR) protection. An interesting result is that Correction Masking also reduces the delay as it adds less logic in the critical path than TMR. Finally, the proposed technique can be used for any syndrome decoder. This means that it is applicable to many of the ECCs used to protect memories such as Single Error Correction (SEC), Single Error Correction Double Error Detection (SEC-DED), Single Error Correction Double Adjacent Error Correction (SEC-DAEC), and 3-bit burst codes.

DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory

This article describes a comprehensive framework for analysis of time-dependent performance-reliability degradation of an SRAM cache, considering cache configurations, process parameters and their variations, supply voltage, and aging. The framework consists of three parts: microprocessor emulation, activity extraction, and evaluation of performance-reliability metrics. Evaluation of performance-reliability metrics is implemented with a prediction engine involving regression models for the metrics, which evaluates degradation due to various wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and random telegraph noise (RTN). The regression models not only enable more than 100× faster computation compared with SPICE simulations but also protect intellectual property. This framework has been applied to study how SRAM instruction cache (I-Cache) configurations, cell structure, inclusion of RTN and gate length variation, voltage scaling, and stress time affect the performance and reliability parameters, such as access time, leakage power, critical charge ( Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> ), and static noise margin (SNM). We have also studied the impact of configuration parameters on the soft error rate (SER) and the hit rate of the I-Cache, and the impact of single error correction and double error detection (SECDED) error correcting codes (ECCs).

Mitigating False Negatives in Harsh Electromagnetic Environments by Combining Complementary Error Detection Codes

In our modern daily lives, more and more electronic systems are performing safety-critical tasks. For these systems, robust communication is crucial. Undetected corruptions of data (a.k.a. False Negatives) within these channels might lead to severe harm to humans or the environment. In order to detect corruptions, Error Detection Codes have since long been used. This letter assesses the resilience of a straightforward duplication mechanism against electromagnetic disturbances by simulating a harsh reverberating electromagnetic environment. The simulations reveal that simply duplicating the bits is not sufficient. By analysing the different fault mechanisms present in duplication, new Error Detection Codes are proposed. These new codes are derived from existing codes, with the explicit requirement to cover each other's vulnerabilities towards False Negatives. In this letter, the EMI-resilient codes are built based on a duplication methodology combined with a Hamming Double Error Detection Code. Due to the different coverage of failure mechanisms under the considered reverberating electromagnetic environment, the rate of False Negatives is significantly reduced.

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes

The work proposes an 11T SRAM cell which confirms its reliability for Internet of Things (IoT) based health monitoring system. The cell executes improved write and read ability using data-dependent feedback cutting and read decoupled access path mechanism respectively. The write and read stabilities of proposed cell are $$2.67\times$$ and $$1.98\times$$ higher than the conventional 6T cell with $$1.53\times$$ area overhead. Moreover, the improved soft error tolerance and better reliability against negative bias temperature instability (NBTI) of proposed 11T SRAM cell as compared to other considered cells make it suitable for the bio medical implant. A low-power double adjacent bit error detection and correction (DAEDC) scheme is proposed to further improve the robustness of designed 1 Kb bit-interleaved memory against the soft error occurrence. The leakage power of proposed cell is controlled by the stacking devices used in its cross-coupled inverter pair and the column based read ground signal (RGND) further controls the unnecessary bit line switching power of the array.

Power efficient error correction coding for on‐chip interconnection links

A configurable self-calibrated power efficient five-bit error correction code is proposed to correct both single bit random and burst errors up to five bits; providing 100% error correction probability with crosstalk avoidance. It can also correct higher-order error up to 9 bits with an error correction probability tolerance of 73% for on-chip interconnection links. Single error correction and double error detection with extended Hamming code (22,16) is utilised along with standard triplication error correction methods in the proposed code. Self-calibration algorithm and data stream rerouting block are integrated into the error correction code to achieve power efficiency. Reliability, link power consumption, and link swing voltage are estimated using an analytical model used in a network-on-chip. Area, power, and delay of the codec are obtained using Synopsys tools utilising UMC 90 nm technology. The proposed method provides 32–73% power saving and 22.3–60.6% delay reduction with negligible area overhead compared with the state-of-the-art works. Estimated results prove that it provides a 40.5–50% reduction in link swing voltage and link power consumption compared with the state-of-the-art works. The proposed code is more appropriate for on-chip interconnect links where it provides high reliability and low swing voltage with high error correction capability compared with existing codes.

Generating nonlinear codes for multi-bit symbol error correction using cellular automata

Error Correcting Codes can be used in cryptography since the security of cryptosystems depends heavily on their resilience against attacks such as fault attacks. In the last three decades, Cellular Automata (CA) have been explored as efficient crypto-primitives as well as to generate error correcting codes. In earlier works, CA are mainly used in bit error correction for Single Error Correcting (SEC) and Double Error Detecting (DED) codes. However, in the practical scenario, when fault is injected by a laser beam or using a clock glitch, multiple bits get infected. The situation thus demands detection/correction of multi-bit errors instead of SEC-DED. In literature, linear CA are used for bit as well as byte error correction. But the CA generating linear codes are of very little use in cryptography as they provide little or no security when used as a component in a cryptosystem. In this paper, linear cellular automata (LCA) with nonlinearity injection at some specific cell positions are used for generating error correcting codes (ECC) which can detect and correct errors in m-bit symbols (m = 8 for a byte). In this paper, we propose coding schemes for single bit as well as multi-bit error correcting codes. For multi-bit error correcting codes, two schemes are proposed. The schemes can easily be extended for generating ECC for different m-bit symbols by simply exploiting m-bit LCA with nonlinearity injection. Moreover, the simple and regular structure of the CA makes the ECC scheme very well suited for VLSI implementation.

2D Parity Product Code for TSV online fault correction and detection

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults. In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code. In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction.

Extended Matrix Region Selection Code: An ECC for adjacent Multiple Cell Upset in memory arrays

With the widespread of electronics nowadays, Single Event Effects (SEEs) have become a significant concern, not only for critical applications like aerospace and military but also for the automotive industry and medical instruments, where reliability is always at a premium. This concern is notable in environments containing ElectroMagnetic (EM) and ionizing radiations, whose interactions with the matter may change the state of memory elements and thus, degrading system reliability. Technology scaling down increases the probability that the strike of a charged particle or a power bus fluctuation due to conducted EM interference affects more than one cell; therefore, resulting in a Multiple Cell Upset (MCU). Single Error Correction–Double Error Detection (SEC-DED) codes are among the most applied techniques to provide reliability to memory systems. However, standard implementations of SEC-DED codes are not suitable anymore to provide information reliability because they cannot satisfactorily handle a considerable number of bit-flips per coded word, i.e., MCU occurrence. In this context, this paper proposes the extended Matrix Region Selection Code (eMRSC), an improved version of MRSC, which extends the original 16-bit code previously published to a new MRSC version of 32 data bits. Additionally, it is proposed a new scheme of data matrix regions for reducing the number of generated redundant bits. The proposed codes were compared to well-known codes, presenting outperforms in all experiments. The synthesis analysis showed that the proposed codes are not only reliable, but they also result in low implementation cost (i.e., low area, coding/decoding delay and power overheads).

Cyclic Properties and Pipeline Implementation of the Fletcher Checksum

The Fletcher checksum (FC) is a means of error detection that is analogous to cyclic redundancy checking but easier to implement in software. Now FC actually has two versions, one is Fletcher's original paper version termed as FC and the other is RFC1146 version termed as FC-RFC. This paper shows that the FC is a cyclic code. This is done by introducing a cyclic code known as the cyclic Fletcher code (CFC) and then showing that the CFC is equivalent to the FC. The clear algebraic structure of cyclic codes is used to analyze the code block length and code distance, and then the single error correction, double error detection, and burst error detection of the CFC are analyzed. Also given is the mathematical relationship between the CFC and a modified FC. Finally, the issue of implementation is considered, and a new scheduling for the CFC is proposed to prevent data hazards. A simulation shows that the proposed scheduling offers improvements of at least 46% in throughput for the CFC and FC-RFC.