Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review

Abstract

Abstract: A 40 MHz with 32-bit and 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic read-modify-write operations. The proposed system implements inorder issuing of instructions. The design includes a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating-point execution units, interrupt controller, error control module, and a UART peripheral. Individual interrupts can have up to four levels of primary priority set in the interrupt controller. For the main memory, the error control module provides single error correction and double error detection. For on-chip communication, the Wishbone B.3 bus standard is used. On a Virtex-7 XC7VX485T FFG 1761-2 FPGA-based board, the processor is implemented. The architecture has CoreMark and Dhrystone benchmark ratings of 3.84/MHz and 1.0603 DMIPS/MHz, respectively