Efficiency Estimation of Single Error Correction, Double Error Detection and Double-Adjacent-Error Correction Codes

Abstract

Failures in memory are a serious problem for ensuring the reliability of spacecraft onboard equipment. To correct errors in memory, Single Error Correction and Double Error Detection (SEC-DED) codes are traditionally used. However, they do not correct multiple errors in the code word, the probability of occurrence of which increases with the development of microelectronic technologies. More recently, a new class of codes Single Error Correction, Double Error Detection and Double-Adjacent-Error Correction (SEC-DED-DAEC) code. However, these codes are not only characterized by increased code word implementation complexity and redundancy, but also by the probability of double non-adjacent error mis-correction. The SEC-DED-DAEC currently includes several codes. In this work, an experimental effectiveness estimation of this class correction codes is carried out, for which a method for evaluating the code was proposed, combining the indicators of redundancy, complexity and DAEC mis-correction probability. Based on the estimation, recommendations are given on the use of specific SEC-DED-DAEC codes in electronic space instrument engineering. The results of the work can be used in the design of fault-tolerant memory, including cryptographic systems for spacecraft. #CSOC1120