Generating nonlinear codes for multi-bit symbol error correction using cellular automata

Abstract

Error Correcting Codes can be used in cryptography since the security of cryptosystems depends heavily on their resilience against attacks such as fault attacks. In the last three decades, Cellular Automata (CA) have been explored as efficient crypto-primitives as well as to generate error correcting codes. In earlier works, CA are mainly used in bit error correction for Single Error Correcting (SEC) and Double Error Detecting (DED) codes. However, in the practical scenario, when fault is injected by a laser beam or using a clock glitch, multiple bits get infected. The situation thus demands detection/correction of multi-bit errors instead of SEC-DED. In literature, linear CA are used for bit as well as byte error correction. But the CA generating linear codes are of very little use in cryptography as they provide little or no security when used as a component in a cryptosystem. In this paper, linear cellular automata (LCA) with nonlinearity injection at some specific cell positions are used for generating error correcting codes (ECC) which can detect and correct errors in m-bit symbols (m = 8 for a byte). In this paper, we propose coding schemes for single bit as well as multi-bit error correcting codes. For multi-bit error correcting codes, two schemes are proposed. The schemes can easily be extended for generating ECC for different m-bit symbols by simply exploiting m-bit LCA with nonlinearity injection. Moreover, the simple and regular structure of the CA makes the ECC scheme very well suited for VLSI implementation.