METHODICAL APPARATUS FOR ENSURING THE CORRECTION OF SINGLE ERRORS AND DETECTION OF DOUBLE ERRORS IN STORAGE DEVICES

Abstract

The analysis of errors that occur during the operation of static storage devices (SD) is carried out. The conclusion is drawn that single and double errors are most likely to occur in memory devices (single errors appear with a probability of up to 80 %, double errors up to 20 – 25 %, and errors of other multiplicity account for up to 2 %). Methods for protecting storage devices from single and double errors are considered. It has been established that at present, for the correction of single errors and the detection of double errors, a modified Hamming code is widely used, which uses for this purpose an additional parity bit for all bits of the code set. The necessity of developing a code that corrects single errors and detects double errors while reducing information redundancy is substantiated. Regularities have been identified that make it possible to form rules for encoding information, and when decoding, to form three additional checks for an error sign to determine erroneous bits in the event of indistinguishable error syndromes. The corrective ability of the proposed method of information coding is investigated. It has been established that the proposed code allows correcting all single errors, detecting all double errors and, at the same time, correcting some of the double errors that simultaneously occur in information and check bits. A regular information coding procedure is described for correcting single and detecting double errors while reducing information redundancy by one check bit and, consequently, reducing hardware costs associated with storing the values of check bits in a memory device. A comparative evaluation of the detection ability and information redundancy of the proposed method with a modified Hamming code is carried out using the example of coding an 11-bit information word. It has been established that for the code (15,11), the implementation of the proposed method makes it possible to detect all single and double errors, correct 100 % of single errors and 27 % of double errors, and use four check digits for these purposes (one less check digit than modified Hamming code). The conclusion is made that the reduction of information redundancy makes it possible to increase the code speed and reduce hardware costs associated with storing the values of a given bit in a memory device and, therefore, increase the probability of failure-free operation and reliability of the memory device operation while reducing information and hardware redundancy.