An Area and Power Efficient Double Adjacent Error Correcting Parallel Decoder based on (24, 12) Extended Golay Code

Abstract

Memory is an integral part in most of the modern electronic gadgets. In these gadgets, reliable memory is very much desired for proper functionality of the whole system. Any issue against the reliability of memory may lead to system failure. One such issue is the radiation-induced soft errors which damage data stored in one or multiple memory cells. Error Correction Codes (ECCs) are generally employed to mitigate the effect of soft errors in memories. In this paper, a new Single Error Correction- Double Error Detection - Double Adjacent Error Correction (SEC-DED-DAEC) code has been proposed based on extended Golay code. Proposed parallel decoder has been designed and implemented both in FPGA and ASIC platforms. Performance of the proposed decoder has been compared with the existing extended Golay parallel decoder for single and double adjacent errors correction. The decoder's performance of the proposed SEC-DED-DAEC code is better in terms of area, delay and power consumption.