Double Data Rate Memory Research Articles

An Efficient Stress Pattern Based on VMRQ-PRBS for DDR Training

With increasing of clock rate and routing density, the problem of signal integrity in high-speed parallel links is becoming increasingly serious. Hence, the design of an effective input/output (IO) stress pattern is necessary in post-silicon testing and validation, which can identify circuit functional bugs quickly and provide adequate test coverage. In this article, an effective stress pattern based on the variable mark ratio quasi-pseudorandom bit sequence is proposed to train the center point of the received signal's eye diagram to obtain the best sampling timing and the reference voltage of double data rate memory. The stress pattern is divided into two parts, i.e., the stress pattern of the victim line that can excite the worst intersymbol interference (ISI) and the stress pattern of the aggressor line that can excite the worst cross talk. To validate the efficiency of the proposed stress pattern, it is compared to the victim–aggressor stress pattern based on pseudorandom binary sequence (PRBS). The measurement comparison shows that the pressure degree of the proposed stress pattern becomes more serious than that of the victim–aggressor stress pattern with increasing data rate.

Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications

Graphics processing units (GPUs) are widely used to accelerate data-intensive applications. To improve the performance of data-intensive applications, higher GPU memory bandwidth is desirable. Traditional graphics double data rate memories achieve higher bandwidth by increasing frequency, which leads to excessive power consumption. Recently, a new memory technology called high-bandwidth memory (HBM) based on 3-D die-stacking technology has been used in the latest generation of GPUs, which can provide both high bandwidth and low power consumption with in-package-stacked DRAM memory. However, the capacity of integrated in-package-stacked memory is limited (e.g., only 4 GB for the state-of-the-art HBM-enabled GPU, AMD Radeon Fury X). In this paper, we implement two representative data-intensive applications, convolutional neural network (CNN) and breadth-first search (BFS) on an HBM-enabled GPU to evaluate the improvement brought by the adoption of the HBM, and to investigate techniques to fully unleash the benefits of such HBM-enabled GPU. Based on the evaluation results, we first propose a software pipeline to alleviate the capacity limitation of the HBM for CNN. We then design two programming techniques to improve the utilization of memory bandwidth for BFS application. Experimental results demonstrate that our pipelined CNN training achieves a $1.63\times $ speedup on an HBM-enabled GPU compared with the best high-performance GPU in market, and the two optimization techniques for the BFS algorithm make it at most $24.5\times $ ( $9.8\times $ and $2.5\times $ for each technique, respectively) faster than conventional implementations.

Analysis of Single-Event Effects in DDR3 and DDR3L SDRAMs Using Laser Testing and Monte-Carlo Simulations

This paper presents a comparative analysis of the single-event effect (SEE) sensitivity of Double Data Rate memories from different manufacturers. Two-photon laser testing is performed to extract technological information such as the memory array organization and an estimation of the cell size. SEE laser energy thresholds are compared as well as the impact of the applied power mode. Bitline upsets are experimentally observed and confirmed by an analysis based on Monte-Carlo simulations. Heavy-ion testing results, including various kinds of SEFIs, are presented and discussed.

Increasing Hyperscale Data Center Efficiency: A Better Way to Manage 54-V\/48-V-to-Point-of-Load Direct Conversion

The hyperspeed growth of data center power demand starts with the high power consumption required by the current and upcoming generations of digital application-specific integrated circuits (ASICs)-central processing unit (CPU), double data rate memories (DDR) and networking ASICs-in addition to the exploding use of high-power graphics processing units (GPUs) for artificial intelligence and machine-learning functions. Hyperscale data centers will also increase in number, from 259 at the end of 2015 to 485 by 2020. They will represent 47% of all installed data center servers by 2020 [1]. Server shipment growth has been driven by large, hyperscale data centers, where servers are often configured for maximum productivity and operate at high utilization rates. Server power consumption is perpetually escalating, and this trend will continue into the near future for both midrange and high-end power servers [2], as shown in Figure 1.

A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs

This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector.

DLL-based 4-phase duty-cycle and phase correction circuit for high frequency clock tree

In high-speed data transmission applications such as double data rate memory and double sampling ADCs, clock generation and distribution circuits must provide the clocks with precise duty cycle of 50% and sufficient timing margin. The proposed DLL-based 4-phase duty-cycle and phase correction circuit, consisting of delay-locked loop (DLL) and 45 phase clock generator (SR latch) corrects distorted duty-cycle clock to 50% duty-cycle. The distorted duty-cycle input clock passes through the DLL. After the DLL is locked, the delay of delay line is identical to the period of input clock. Lastly, 4-phase, 50% duty-cycle clocks is generated from the combination of rising edges of signals at each 1/4 points of delay line. The proposed circuit is implemented in 65nm CMOS. The simulation results shows that the frequency range of the proposed circuits is 550-1600MHz, the maximum duty cycle error of the output clock can be less than 1% with the input duty cycle correction ranging from 25% to 80%. The phase difference with the 4-phase output clock is 250±3ps at a frequency of 1GHz. The measured power dissipation is 4.3mW.

A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

A system clock with a 50% duty cycle is demanded in high-speed data communication applications, such as double data rate memories and double sampling analog-to-digital converters. In this paper, a wide-range low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line to reduce the required length of the delay line to half of the input clock period. Thus, it can extend the operating frequency toward a lower frequency with small area cost as compared with the conventional design. The proposed design is implemented in a standard performance 90-nm CMOS process, and the active area is $170\times 170~\mu $ $\mathrm{m}^{2}$ . The input frequency of the proposed ADDCC ranges from 75 to 734 MHz, and the input duty-cycle ranges from 9% to 86%. The measured output duty-cycle error is less than 1.78%. The proposed ADDCC consumes 4.59 mW at 734 MHz and 0.9 mW at 75 MHz with a 1.0-V power supply.

A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization

High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately -170 for (1)H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo (1)H MRI at 0.35 T.

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

In high-speed data transmission applications, such as double data rate memory and double sampling analog-to-digital converter, the positive and negative edges of the system clock are utilized for data sampling. Thus, these systems require an exact 50% duty cycle of the system clock. In this paper, two wide-range all-digital duty-cycle correctors (ADDCCs) with output clock phase alignment are presented. The proposed phase-alignment ADDCC (PA-ADDCC) not only achieves the desired output/input phase alignment, but also maintains the output duty cycle at 50% with a short locking time. In addition, the proposed high-resolution ADDCC (HR-ADDCC) without a half-cycle delay line can improve the delay resolution and mitigate the delay mismatch problem in a nanometer CMOS process. Experimental results show that the frequency range of the proposed ADDCCs is 263-1020 MHz for the PA-ADDCC and 200-1066 MHz for the HR-ADDCC with a DCC resolution of 3.5 and 1.75 ps, respectively. In addition, the proposed PA-ADDCC and HR-ADDCC are implemented in an all-digital manner to reduce circuit complexity and leakage power in advanced process technologies and, thus, are very suitable for system-on-chip applications.

Modeling and Fast Eye Diagram Estimation of Ringing Effects on Branch Line Structures

Significant ringing effects due to multiple reflections are first addressed for the slightly unbalanced address lines in the double data rate memory systems. A resistance-inductance-capacitance resonance model is proposed to explain its occurrence by fitting the transfer function in frequency domain. The transient analysis can then be performed easily and the peak distortion analysis is used to predict its eye height. The cases with the worst signal integrity were identified and a simple design rule is derived to avoid its occurrence, which is dependent on the attenuation constant of the transmission line and the data rate of the signal.

Programmable DDRx Controllers

Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable. Unfortunately, the stringent latency and throughput requirements of modern DDRx (double data rate memory interface technology) devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware. Pardis is the first programmable memory controller that can meet these challenges and thus satisfy the performance requirements of a high-speed DDRx interface.

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories

This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows thp smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400MHz operation with CL=2.5.

Memory subsystem technology and design for the z990 eServer

This paper discusses the technology and design of the first double data rate (DDR) memory subsystem for the IBM zSeries® eServer™. The main storage subsystem accommodates the frequency mismatch between the memory controller and industry-standard synchronous dynamic random-access memory (SDRAM), protects data through error-correction code and SDRAM sparing, and increases overall memory subsystem bandwidth. Each memory card consists of the first synchronous memory interface (SMI) application-specific integrated circuit (ASIC) that is optimized specifically for DDR applications, the SMI-enhanced (SMI-E). The SMI-E controller data interface communicates with the high-speed memory controller on the multichip module through special phase alignment and elastic buffering circuitry that determines the optimal sampling point to reliably receive data from the controller. The SMI-E memory data interface is connected to registered DDR dual inline memory modules running up to 250 Mb/s using 256-Mb and 512-Mb SDRAM technology, thereby allowing memory card densities between 4 GB and 32 GB per card. Because of the increased DDR memory interface bit rates, special attention was paid to the design of the SMI-E substrate and base card to minimize noise. The memory, when used in a fully populated system, has four times more storage capacity than the previous z900 generation.