An Efficient Stress Pattern Based on VMRQ-PRBS for DDR Training

Abstract

With increasing of clock rate and routing density, the problem of signal integrity in high-speed parallel links is becoming increasingly serious. Hence, the design of an effective input/output (IO) stress pattern is necessary in post-silicon testing and validation, which can identify circuit functional bugs quickly and provide adequate test coverage. In this article, an effective stress pattern based on the variable mark ratio quasi-pseudorandom bit sequence is proposed to train the center point of the received signal's eye diagram to obtain the best sampling timing and the reference voltage of double data rate memory. The stress pattern is divided into two parts, i.e., the stress pattern of the victim line that can excite the worst intersymbol interference (ISI) and the stress pattern of the aggressor line that can excite the worst cross talk. To validate the efficiency of the proposed stress pattern, it is compared to the victim–aggressor stress pattern based on pseudorandom binary sequence (PRBS). The measurement comparison shows that the pressure degree of the proposed stress pattern becomes more serious than that of the victim–aggressor stress pattern with increasing data rate.