Contact Doping Research Articles

Lateral current injection lasers: underlying mechanisms and design for improved high-power efficiency

The lateral current injection (LCI) laser-a promising technology for enabling optoelectronic integrated circuits and photonic devices with novel functionalities-is studied by comparison with conventional vertical injection devices. Fully self-consistent two-dimensional (2-D) simulations of lateral and vertical lasers reveal physical effects unique to the lateral injection class of devices. We find that (1) strong lateral carrier confinement is critical to efficient LCI laser operation, even if the active region is wide, in view of ambipolar effects, (2) current paths in parallel with the active region, even if they consist of high-bandgap intrinsic material, may nevertheless admit significant parasitic leakage even at moderate injection levels, and (3) a straightforward, but powerful, solution to the problem of premature roll-off in lasing efficiency may be achieved via heavy contact doping without significantly increasing modal free-carrier absorption.

Negative luminescence from In 1− xAl xSb and Cd xHg 1− xTe diodes

Indium aluminium antimonide (In 1− x Al x Sb) and cadmium mercury telluride (Cd x Hg 1− x Te) heterostructure diodes, which comprise a near intrinsic active region bounded by more highly doped contact regions, exhibit positive or negative luminescence at medium to long infrared wavelengths when forward or reverse biased respectively at room temperature. In reverse bias, the carrier densities in the near intrinsic region are reduced below their equilibrium values by the effects of exclusion and extraction. In consequence, the radiative recombination is reduced and the devices emit less infrared radiation than the thermal equilibrium value. The observed intensity of the negative luminescence is in general agreement with expected values.

Blue‐Green ZnSe Laser Diodes for Optoelectronics. Present State at Würzburg University

AbstractA review is given on the research activities at Würzburg University in the field of blue‐green emitting ZnSe laser diodes. Of great importance for both the structural and electrical properties is the possibility to grow a GaAs buffer layer on the GaAs substrate prior to the II–VI growth. Pulsed room temperature lasing with a duty cycle up to 17% is obtained using quaternary ZnMgSSe cladding layers, ternary ZnSSe waveguides, and a single CdZnSe quantum well. Important issues for long‐term stability of such laser diodes like growth start, p‐type doping, and ohmic contacts are discussed.

Evaluation of Ti and TiN thicknesses for tungsten plug contact metallization

A statistical experimental design has been succesfully used to evaluate the integration of CVD tungsten plugs into a PVD-Ti/TiN/AlSiCu metallization. Optimum titanium (Ti) and titanium nitride (TiN) layer thicknesses for tungsten filled contacts with aspect ratios of up to 1.8 have been determined with respect to contact resistance and leakage current data in both n + and p + contacts. Ti thickness (10–50 nm), TiN thickness (50–150 nm) and contact depth (1050–1500 nm) were each varied in three levels and the corresponding responses were investigated for contacts with different diameter. The investigations show that for given contact dimensions, contact resistance is only determined by the Ti thickness. In order to achieve lowest contact resistances even in the contacts with highest aspect ratios, the nominal Ti thickness should at least be 40 nm. A deficiency in Ti, which causes higher contact resistivities, cannot be compensated by an increase of TiN thickness. These results are independent of contact doping. TiN thickness is the most relevant parameter with respect to barrier integrity. However, CVD tungsten filled contacts with a TiN barrier of nominally only 50 nm thickness exhibited lowest leakage currents and also did pass an electrical stress test (1000 h, 150°C, 1.9 × 10 6 A/cm 2), even if the aspect ratio was 1.8 TEM investigations are in agreement with these electrical data although they reveal that the effective barrier thickness is only approximately 10% of the nominal value in contacts with aspect ratio 1.4. Based on these results it is concluded that contact filling with CVD tungsten will be a viable and reliable metallization for sub-0.5-μm technology, especially if improved Ti- and TiN-deposition methods (like, e.g., collimated PVD or conformal CVD) are available.

Microgun-pumped semiconductor laser

We demonstrate the feasibility of a novel microgun-pumped semiconductor laser. This is the most compact (a few cm3) and the lowest threshold electron-beam-pumped semiconductor laser ever reported. The electron source is provided by a 104–105/mm2 array of field emissive microtip cathodes each of 1.5 μm diam. The laser operates below 10 kV and below 1 A/cm2. Laser action in a quasi-cw mode with 5 μs pulses at 2 kHz has been obtained between 90 and 300 K with CdTe-CdMnTe graded index separate confinement quantum-well heterostructures, as well as with GaAs-GaAlAs structures. Since neither doping nor ohmic contacts are needed, the microgun laser can use all direct gap semiconductors. It appears as a viable solution for making compact II-VI lasers in the visible domain.

Enhanced mobility top-gate amorphous silicon thin-film transistor with selectively deposited source/drain contacts

Amorphous silicon thin-film transistors (TFTs), in a top-gate staggered electrode structure have been prepared using selectively deposited doped silicon contact layers, formed in-situ by plasma-enhanced chemical vapor deposition (PECVD). Selective deposition reduces the number of processing steps and assures the formation of low-resistance contacts. Devices fabricated with two photomasks and one plasma deposition step show saturation and linear mobilities as high as 1.1 and 0.9 cm/sup 2//V-s, respectively, with threshold voltages between 3 and 6 V. On/off ratios are >10/sup 6/, with a subthreshold slope of 0.8 V/decade. The mobilities are at least a factor or 2 higher than previously reported for top-gate structures and are similar to values reported for bottom-gate (inverted staggered) TFTs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Quantum box resonant tunneling spectroscopy: Experiments and modelisation

We have calculated the potential profile and the electronic levels in resonant tunneling double barrier structures with nanometric lateral dimensions (≤ 500 nm) for various contact doping. At biases for which the box states (laterally confined quantum well) are resonant with the emitter Fermi level, fine structures are expected in the resonant tunneling current. Comparison with I(V) characteristics measured on nanometric GaAs/GaAlAs and GaAs/GaAlAs/InGaAs resonant tunneling diodes shows that our model accounts for the resonance bias voltage and explains the shape of the current peak. The fine structure observed in the current peak provides a spectroscopy of the confined states in the quantum box.

Optimization of the AlInAs growth temperature for AlInAs/GaInAs HEMTs grown by MBE

The material characteristics of MBE grown AlInAs layers relevant to AlInAs/InGaAs HEMTs, such as surface morphology and specific resistivity, and doping and Schottky contact behaviour, have been investigated in dependence of the growth temperature. Respective optimum results were obtained at different temperatures which were adopted for the growth of HEMT structures. Preliminary results on 1 ?m gate length devices are presented.

High-reliability GaAs-AlGaAs HBTs by MBE with Be base doping and InGaAs emitter contacts

The authors have developed a modified MBE growth process to produce high-gain n-p-n GaAs-AlGaAs heterojunction bipolar transistors (HBTs) with a mean time to failure (MTTF) of 1.5*10/sup 8/ h at 125 degrees C. Beryllium incorporation and diffusion are controlled through a combination of reduced substrate temperature and increased As/Ga flux ratio during MBE growth, resulting in extremely stable HBT profiles. The authors also demonstrate graded InGaAs surface layers with nonalloyed refractory metal contacts that significantly improve ohmic reliability compared to alloyed AuGe contacts. The ability to produce robust HBTs by MBE is critically important to this technology. >

Stacked Si-bipolar diodes with lateral polycrystalline inter-connections grown by two-step MBE

Individually addressed Si-bipolar diodes stacked monolithically in two planes were fabricated, applying a variety of novel technologies. A two-step differential Si-MBE process allows us to grow monocrystalline devices embedded in a poly-Si surrounding which provides lateral or vertical isolation and buried interconnections. The doping levels of the active devices ( n, p ≲ 10 17 cm −3) are concomitant with a high resistivity poly surrounding (10 4-10 5 Ω cm), while highly doped contact layers (> 10 19 cm −3), grown between the two device levels and above the second level are of low resistivity in the monocrystalline (10 −3-10 −1 Ω cm) and in the poly area (10 −2−5 × 10 −1 Ω cm). MBE-growth was interrupted after deposition of the intermediate contact layer to define interconnections by photo-lithography, which were subsequently overgrown by a second MBE process. Patterning of the highly conductive cap layer and etching of contact holes to the by now buried leads permits electrical access to both device levels. The measured device characteristics demonstrate the feasibility of the concept, which also appears very attractive for three-terminal devices. Routes towards optimized growth and doping sequences are discussed.

Influence of the boundary between monocrystalline and polycrystalline silicon on the electrical characteristics of diodes grown by differential MBE

The differential MBE technique is suggested as a tool for separation or interconnection of advanced devices on a common chip. Bipolar diodes with various diameters of 23 to 800 mu m were fabricated and their electrical behaviour measured. Implantation of etching methods were used to eliminate the influence of a highly doped contact layer on top of the epitaxial layer sequence. Leakage currents from 10-7 to 10-9 A are slightly higher than those of reference mesa diodes. It is estimated that the differential technique is applicable to many advanced devices for planar integration.

Carrier transport effects on the photocurrent spectra of an intrinsic GaAs/AlGaAs multiple quantum well with highly doped AlGaAs contact layers

In this study, we demonstrate how electroreflectance (ER) measurements as a function of bias, and of angle of incidence ( θ 0), together with bias dependent photocurrent (PC) measurements, can be used to provide understanding of the complex electric field profile and carrier transport effects in a GaAs/Al 0.3Ga 0.7As multiple quantum well (MQW), grown inside n + contact layers. The PC measurements exhibit split excitonic features, the components of which change in strength with the applied bias. The effect is explained by absorption in the front of the MQW stack, with the back of the stack acting as detector. We examine the θ 0-dependence of the ER lineshape, to determine the depth of the layers responsible for each feature. The ER and PC lineshapes and their bias dependence are explained by the unusual electric field profile across the stack. The field profile appears to be determined by tunnelling of the dark current.

Correlation Between the Interfacial Nonuniformity and the Specific Contact Resistance of Ohmic Contacts to Gaas

ABSTRACTConsidering the effect of the simultaneous presence and interaction of the different phases at the contact, a modification of the model presented by Wu and coworkers (Solid-St. Electron. 29 (1986) 489] for explanation of ohmic contact resistance of n-GaAs was developed. The modified model combines the existence of the mixed phase structure of AuGeNi/n-GaAs contact with assumptions proposed by Wu et al. that the specific contact resistance Rc contains two parts Rcl and Rc2, where Rc1 is the specific contact resistance of the alloyed and underlaying doped contact region, and Rc2, is that of the high-low junction between the heavily doped contact region and the bulk semiconductor. The Rc1 depends strongly on the apparent barrier height and the effective impurity concentration formed by doping from the contact alloys during annealing. In the present paper a new theoretical model for Rc1 is proposed and compared with the experimental results.

Noise performance of submicrometer AlInAs-GaInAs HEMTs

Record DC and RF performance of AlInAs-GaInAs lattice matched to InP HEMTs (high-electron-mobility transistors) with nominally 0.2- and 0.1- mu m gate lengths have been achieved. The devices were fabricated on material grown by MBE (molecular-beam epitaxy) on Fe-doped InP substrates. The epitaxial layers consisted of an undoped AlInAs spacer, a highly doped AlInAs donor layer, an undoped Schottky-enhancing AlInAs layer, and, finally, a highly doped GaInAs layer contact layer. 50- mu m-wide devices with 0.2- and 0.1- mu m-long T-gates were fabricated. The 0.2- mu m gate-length devices were tested at V-band. The single-stage amplifier (waveguide to waveguide with no correction) exhibited a minimum noise figure F/sub min/ of 1.8 dB with an associated gain 7.5 dB at 63.0 GHz. This translates to an amplifier noise measure of 2.10 dB. The corresponding device performance was a minimum noise figure of 1.4 dB with an associated gain of 8.5 dB. This corresponds to a device noise measure of 1.6 dB.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Tungsten chemical vapor deposition characteristics using SiH4 in a single wafer system

Several workers have recently begun using silane as a high-rate, low-temperature alternative to hydrogen for the reduction of WF6 in the chemical vapor deposition of W. The deposition and film characteristics of both selective and blanket W using this new chemistry are explored in a radiantly heated single wafer system using closed-loop temperature control with a thermocouple in direct contact with the backside of the wafer. Selective W deposition rates of up to 1.5 μm/min were measured over the temperature range 250–550 °C with blanket W rates typically 2–5× lower. Resistivity is in the 10–15 μΩ cm range at 300 °C for SiH4/WF6 ratios of 0.2 to 1.0, while above 400 °C the range is 7.5–8.5 μΩ cm. Si content in the W films is quite low at 1016 to 1017 atoms/cm3. Adhesion to silicon is excellent at temperatures of 350 °C and above. Selective W using SiH4 reduction for doped silicon contact fill shows none of the consumption or encroachment problems common to H2 reduction, although selectivity is more sensitive. Contact resistance for p+ and n+ silicon contacts are comparable to aluminum controls and to previously published data. Blanket deposition into narrow geometries gives ≥90% step coverage and without keyholes in the 250–450 °C deposition temperature range. For low-SiH4 flows, deposition at 500 °C causes small keyholes, while at 550 °C even larger keyholes result. At higher SiH4 flows, keyholes are typically not seen from 250 to 550 °C. The SiH4-reduced films are much smoother as indicated by reflectivities that are 2–4×higher than for the H2-reduced films.

Band offsets, Fermi levels and impurity bands in doped contact layers

A Hartree-Fock model for impurity bands is used to obtain a simple, approximate correction to the free electron model which is almost universally used in treatments of doped contact layers in quantum well, heterojunction and modulation doped devices. The operation of such devices depends critically on band offsets and Fermi levels. The model incorporates exchange interactions as well as screening and it is analytically solvable. The results are cast in such a form as to facilitate use in modeling the effect of contact layers in the aforesaid devices. Numerical results for shallow dopant band offsets in GaAs are found to be about 10%–25% of the Fermi energy.

Comment on "NMOS ring oscillators with Cobalt-Silicided P-diffused shallow junctions formed during the 'poly-plug' contact doping cycle"

Composite silicided source-drains are being developed to provide low-resistance shallow junctions for high performance fine-line circuits. The junctions are usually formed either by implantation and drive prior to silicide formation or else by implantation immediately after, followed by a heat cycle. This paper describes a novel approach for the fabrication of CoSi 2 /n+-p junctions (2 . 5 Ω/□ sheet resistance), wherein the junctions are doped by diffusion through the contact windows using the conventional "poly-plug" doping cycle [1], [2]. LPCVD poly-Si is deposited on windows to previously silicided gate and source-drain regions, and exposed to PBr 3 at an elevated temperature. Since the diffusivity of dopants in silicides is higher than in bulk Si, this step transports the P through the poly-Si via the windows laterally into the silicide, to form uniformly doped junction surrounds. This poly-Si doping scheme for junction fabrication eliminates an ion-implant step, provides an independent means of tailoring channel length, and can potentially result in low-resistance contacts even if the window etch step has punched through the silicide, Electrical characteristics of 1.25-µm gate-length ring oscillators are similar to those of circuits processed with the conventional As implant and drive. Transistor I-V 's and subthreshold behavior remain unaffected by the silicide doping process. Junction depth and leakage are sensitive functions of the poly-plug thermal cycle, with a 950°C 30-min drive resulting in 0.3-µm junctions. For a 1-µm design rule circuit layout, 30 to 45 min at 950°C is judged adequate.

NMOS Ring oscillators with cobalt-silicided P-diffused shallow junctions formed during the "Poly-plug" contact doping cycle

Composite silicided source-drains are being developed to provide low-resistance shallow junctions for high performance fine-line circuits. The junctions are usually formed either by implantation and drive prior to silicide formation or else by implantation immediately after, followed by a heat cycle. This paper describes a novel approach for the fabrication of CoSi 2 /n+-p junctions (2 . 5 Ω/□ sheet resistance), wherein the junctions are doped by diffusion through the contact windows using the conventional doping cycle [1], [2]. LPCVD poly-Si is deposited on windows to previously silicided gate and source-drain regions, and exposed to PBr 3 at an elevated temperature. Since the diffusivity of dopants in silicides is higher than in bulk Si, this step transports the P through the poly-Si via the windows laterally into the silicide, to form uniformly doped junction surrounds. This poly-Si doping scheme for junction fabrication eliminates an ion-implant step, provides an independent means of tailoring channel length, and can potentially result in low-resistance contacts even if the window etch step has punched through the silicide, Electrical characteristics of 1.25-µm gate-length ring oscillators are similar to those of circuits processed with the conventional As implant and drive. Transistor I-V 's and subthreshold behavior remain unaffected by the silicide doping process. Junction depth and leakage are sensitive functions of the poly-plug thermal cycle, with a 950°C 30-min drive resulting in 0.3-µm junctions. For a 1-µm design rule circuit layout, 30 to 45 min at 950°C is judged adequate.

Contact resistance: Al and Al–Si to diffused N+ and P+ silicon

Prealloy and postalloy contact resistances at [(Al–Si)/bulk (100)Si] interfaces have been measured for a range of Al–Si alloy compositions (0–2 at.% Si), alloying temperatures (325–550 °C), and contact sizes (3–5 μm). Contact doping for n+/p junctions was by diffusion from a POCl3 source; for p+/n junctions, by diffusion from a BN source. Al–Si deposition was by S–Gun■ magnetron sputtering. Statistical distributions of prealloy contact resistance to n+ Si were found to provide highly sensitive monitors of contact cut and deposition-system cleanliness.. Minimum postalloy contact resistance values were independent of Al–Si alloy composition, and silicon pitting in the contact cut was not required to achieve good Ohmic contact. The maintenance of consistent, low-resistance Ohmic contacts throughout postalloy processing was found to depend on the silicon concentration in the aluminum being high enough to keep the aluminum supersaturated during all postdeposition temperature cycling.

Models for ohmic contacts on graded crystalline or amorphous heterojunctions

A one-dimensional model for sandwich-type graded heterojunctions is presented to explain the formation of contacts that cannot be based on highly doped contact layers, such as indium contacts to GaAs and GaSb. In this model a hyperbolic dependence on distance for the permittivity and a constant space charge density owing to filled interferance states is assumed. Algebraic solutions have been obtained for the barrier height and capacitance of a wide variety of heterojunctions. The conditions for zero barrier height, i.e. ohmic contacts, are discussed. The graded heterojunction model is also applied to heterojunctions formed by an amorphous and a crystalline semiconductor to explain the formation of ohmic contacts in cases where neither doping nor crystalline heterojunction effects can be assumed, such as Au, Ag, InAu, InAg and AuNi metal contacts to GaAs, GaSb or GaP.