Enhanced mobility top-gate amorphous silicon thin-film transistor with selectively deposited source/drain contacts

Abstract

Amorphous silicon thin-film transistors (TFTs), in a top-gate staggered electrode structure have been prepared using selectively deposited doped silicon contact layers, formed in-situ by plasma-enhanced chemical vapor deposition (PECVD). Selective deposition reduces the number of processing steps and assures the formation of low-resistance contacts. Devices fabricated with two photomasks and one plasma deposition step show saturation and linear mobilities as high as 1.1 and 0.9 cm/sup 2//V-s, respectively, with threshold voltages between 3 and 6 V. On/off ratios are >10/sup 6/, with a subthreshold slope of 0.8 V/decade. The mobilities are at least a factor or 2 higher than previously reported for top-gate structures and are similar to values reported for bottom-gate (inverted staggered) TFTs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>