Doped Buffer Layer Research Articles

Spontaneous Conversion of Basal Plane Dislocations in 4° Off-Axis 4H–SiC Epitaxial Layers

The conversion of basal plane dislocations (BPDs) to electrically benign threading edge dislocations in 4° off-axis 4H–SiC epilayers has been investigated using ultraviolet photoluminescence imaging. The conversion spontaneously occurred throughout the epitaxial layer for all substrates studied using similar epitaxial growth conditions. BPD conversion in highly doped epilayers was suppressed compared with lower n-type doped layers, suggesting that nitrogen concentration influences the conversion mechanism. However, it is technologically important for the conversion to occur in a heavily doped buffer layer. The densities of BPDs in low-doped (∼1014 cm–3) films having a thickness of 20 μm were significantly reduced when a ∼20 μm thick highly doped N+ buffer layer was grown between the low-doped layer and the substrate. Without the buffer layer, an average of ∼50 BPDs cm–2 was observed and with the buffer layer, an average of 1.5 BPDs cm–2 was detected; the best result was 0.2 BPD cm–2. A PiN structure consisting of a 25 μm thick N+ buffer layer to convert the majority of BPDs prior to the device structure was used to test the mitigation process, and the diodes demonstrated no forward voltage change after 225 h of continuous biasing at 100 A cm–2.

Innovative Solutions to Materials Challenges for High-Voltage SiC Power Devices

Silicon carbide (SiC) is a material of interest for high-temperature, high-voltage and high-power switching device applications. Key materials challenges inhibiting such devices include elimination of basal plane dislocations (BPDs) and enhancement of minority carrier lifetimes in the drift or blocking regions of the device. Recent progress in addressing both of these issues is presented. BPDs are a major concern for the SiC bipolar devices required for high-voltage applications as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes. Many methods have been investigated to reduce the BPD density including pre-growth treatments, substrate orientation, growth parameters and growth interrupts. It has been shown that the conversion of BPDs to threading edge dislocations (TEDs) continues throughout the epitaxial growth process in 4° off-axis SiC material and that a minimum thickness of ~16 µm is required to convert all BPDs to TEDs. Here we show that optimizing a hydrogen etch of the substrate prior to epitaxial growth significantly enhances conversion efficiency in a thin highly doped n+ buffer layer (BL). IN this work, epitaxial layers were grown on 4° off-axis substrates in an Aixtron/Epigress VP508 horizontal hot-wall reactor using the standard chemistry of silane (2% in H2) and propane. In addition, using various growth approaches, low-doped epitaxial layers of only 20 µm in thickness on a 5 µm highly doped buffer layer have demonstrated minority carrier lifetimes up to 4 µs, as measured by time resolved photoluminescence, without any pre- or post- processing treatment. Interface recombination likely dominates these measurements. We extend this approach by presenting new data investigating the non-uniformity of lifetime found on as-grown material under various conditions.This work is supported by the Office of Naval Research

Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress

We evaluate the stacking faults (SFs) expansion from basal plane dislocations (BPDs) converted into threading edge dislocations (TEDs) under the current stress to the pn devices and analyzed the nucleation site of the SF by combined polishing, chemical etching in molten KOH, photoluminescence imaging, Focus ion beam, transmission electron microscopy, and Time-of-Flight secondary ion mass spectrometer techniques. It was found that the formation of SFs occurs upon the current stress levels of 400 A/cm2 where the diode area is not including BPDs in the drift layer after the high current stress, and the high current stress increases the SFs expansion density. It was also found the dependence of the junction temperature. The estimated activation energy for the expansion of SFs is Ea = 0.46 eV. The SF extends from the conversion point of the BPD into the TED within buffer layer. Even though BPDs converted into TEDs within the high doped buffer layer, SFs expand under high current stress.

Observation of stacking faults from basal plane dislocations in highly doped 4H-SiC epilayers

Stacking fault (SF) expansion from basal plane dislocations (BPDs) confined in highly doped 4H-SiC buffer layers is observed under high-power ultraviolet illumination (>1000 W/cm2). Once the SFs reach the active drift layers, grown above the buffer layers, they are seen to rapidly expand up to the sample surface where they can cause device degradation. BPD faulting in the buffer appears to have a carrier injection threshold. Carrier density simulations under various injection conditions and carrier lifetimes are used to establish the conditions of BPD faulting within the buffer layer that could prevent SF expansion into the drift layer.

Numerical Simulation of 4H-SiC Metal Semiconductor Field Transistors

This work simulates the performance of 4H-SiC MESFETs and establishes the optimum device structure for dc and rf applications that operate at high voltages. Devices with various channel doping, buffer layer doping, recess thickness, gate-to-drain spacing and temperatures of operation are considered. The simulation results reveal that a p-type buffer layer of 5×1015 cm−3 and a channel layer of 1×1017 cm−3 yield favorable results. The cut-off frequency is 22.53 GHz, the maximum transconductance is 50.55 mS/mm, the drain saturation current is 239.76 mA/mm and the breakdown voltage is 70.40 V. The breakdown voltages increase to 90.2 V as the gate-to-drain spacing increases to 1 μm. Based on these simulation results, new 4H-SiC MESFET designs can be calibrated.

Investigation of generation-recombination centres of Au/n-GaAs Schottky diodes with InAs self-assembled quantum dots

Capacitance and reverse current–voltage measurements have been performed as a function of temperature on Au/n-GaAs Schottky diodes with InAs quantum dots (QDs) embedded between two GaAs spacers. The spacers were either doped or undoped containing a QD layer equivalent to 3 monolayer (ML) QD coverage. In the investigated temperature range of 77–350 K and for all the diodes measured, the apparent free electron concentration close to the QDs layer is lower compared to the concentration at the interface between GaAs doped buffer layer and GaAs n +-substrate, showing that the QDs induce more traps than those created at a conventional interface. Theoretical fitting of the capacitance–voltage characteristics yields the values of the energy level, the sheet concentration and the dispersion of the distribution of the confined states induced by the InAs quantum dots, which is higher for the diode with doped GaAs spacers than for the diode with undoped spacers. The effective activation energies of the traps, obtained from the effective generation lifetime calculated from reverse voltage current, agree well with the results obtained from the theoretical fitting.

Glycerol-Doped Poly(3,4-ethylenedioxy-thiophene):Poly(styrene sulfonate) Buffer Layer for Improved Power Conversion in Organic Photovoltaic Devices

We investigated the influence of glycerol doping to poly(3,4-ethylenedioxy-thiophene):poly(styrene sulfonate) (PEDOT:PSS) on the power conversion efficiency (PCE) of the bulk heterojunction photovoltaic cells using poly(3-hexylthiophene) and phenyl-C61-butyric acid methyl ester. In particular, a correlation between PCE and changes in the conductivity, surface morphology, contact properties, and work function of glycerol-doped PEDOT:PSS(G-PEDOT:PSS) was investigated as a function of an added glycerol ratio. The PCE was increased from 2.5 to 3.3% by using the optimum glycerol doping ratio. It is believed that the improved PCE of the photovoltaics is possibly due to the increased short-circuit current from the enhanced hole carrying ability as well as the enlarged contact area of the doped buffer layer.

A Novel Super-Junction Lateral Double-Diffused Metal—Oxide—Semiconductor Field Effect Transistor with n-Type Step Doping Buffer Layer

A novel super-junction lateral double-diffused metal–oxide–semiconductor field effect transistor (SJ-LDMOSFET) with n-type step doping buffer layer is proposed. The step doping buffer layer almost completely eliminates the substrate-assisted depletion effect, modulates lateral electric field and achieves nearly uniform surface field. On the other hand, the buffer layer also provides another conductive path and reduces on-state resistance. In short, the proposed LDMOSFET improves trade-off performance between breakdown voltage (BV) and specific on-state resistance Ron,sp. Compared with the conventional SJ-LDMOSFET, the simulation results indicate that the BV of the SSJ-LDMOSFET is increased from saturation voltage 121.7V to 644.9V; at the same time, the specific on-state resistance is decreased from 0.314Ω·cm2 to 0.14Ω·cm2 by virtue of 3D numerical simulations using ISE when the drift region length and the step number are taken as 48μm and 3, respectively.

Enhanced thermal stability in organic light-emitting diodes through nanocomposite buffer layers at the anode/organic interface

The effect of doped buffer layers at the anode/organic interface in small molecule organic light-emitting diodes was investigated. Appropriate doping of N,N′-bis(1-naphthyl)-N,N′-diphenyl-1,1′-biphenyl-4,4′-diamine (NPB) and Cu-phthalacyanine (CuPc) layers using LiF or C60 molecules leads to improved interfacial morphology and thermal stability for both standard indium tin oxide or metals anodes, such as Au and Ag. Graded interfaces remain stable at temperatures well above the hole transport layer (i.e., NPB) glass transition temperature.

Ion Beam Induced Charge characterization of epitaxial single crystal CVD diamond

IBIC (Ion Beam Induced Charge) technique has been used in order to characterize single crystal epitaxial CVD diamond film with respect to homogeneity and stability of the response (in terms of charge collection efficiency, cce) as a function both of counting rate and of the number of counts per unit surface area. The maximum shift of cce peak, under a 1.2 MeV proton microbeam, is 1.5% for counting rates from 43 to 4330 Hz, while the homogeneity, evaluated as the standard deviation with respect to the average value of cce over strip-like regions 60–100 μm wide and 800–1200 μm long, is 0.5%. Counting rates per unit surface area were between 30 and about 15,000 Hz/mm 2. A total number of counts per unit area up to 9 10 6 counts/mm 2 was reached without noticing any polarization effect due to trapped charge. Moreover, the functionality of a new kind of bulk electrode, realized by a boron doped buffer layer laterally contacted with Ag paste, has been checked by measuring cce at different proton ranges.

Fabrication of AlGaN/GaN HFET with a High Breakdown Voltage on 4-inch Si (111) Substrate by MOVPE

ABSTRACTWe investigated an AlGaN/GaN heterostructure field effect transistor (HFET) on Si substrates using a multi-wafer metalorganic vapor phase epitaxy (MOVPE) system. It was confirmed that a GaN film with smooth surface and without any crack was obtained. To increase a resistance of a GaN buffer layer, the carbon (C) -doping was carried out by controlling the V/III ratio and the growth pressure. The breakdown voltage of the buffer layer was dramatically improved by introducing the C. As a result, the breakdown voltage was about 900 V when the C concentration was about ∼8×1018 cm−3. After while, an AlGaN/GaN heterojunction FET (HFET) on a C-doped GaN buffer layer was fabricated. We achieved the breakdown voltage of over 1000 V and the maximum drain current of over 150 mA/mm, respectively. It was found that the C doped buffer layer is very effective for improving the breakdown voltage of AlGaN/GaN HFETs.

EFFECTS OF BUFFER LAYER THICKNESS AND DOPING CONCENTRATION ON SiC MESFET CHARACTERISTICS

Two-dimensional simulations have been carried out using the Atlas® device simulator to investigate the effects of the buffer layer thickness and doping concentration on the electrical characteristics of the SiC MESFET. The variations of transconductance, output resistance, gate-source capacitance, gate-drain capacitance and (cutoff frequency) f T with respect to the change in buffer layer thickness and doping concentration have been investigated. It is observed that the performances of MESFET can be improved by reducing the leakage of channel carrier into the substrate at high drain bias, which is achieved by increasing buffer layer doping density and/or increasing buffer layer thickness. For a SiC MESFET with buffer layer thickness of 0.3μm and gate length of 1μm, drain current increases from 0.1A/ μm to above 0.45A/ μm as the buffer layer doping density is decreased from 1.9 × 1017 cm -3 to 1 × 1016 cm -3. The simulations were carried out at a gate-source voltage of –1V and a drain-source voltage of 15V. Under similar conditions, the output resistance decreases from 1.2 × 106 Ω/μ m to 1.2 × 106 Ω/μ m , and the transconductance decreases from 5.9mS/ μm to 5.3mS/ μm, and f T decreases from 11GHz to 8GHz.

Computational load pull simulations of SiC microwave power transistors

The design of power transistors for microwave applications requires a good understanding of their large signal behaviour in a real circuit context. The computational load-pull simulation technique is a powerful new way to evaluate the full time-domain voltages and currents of microwave power transistors during realistic operation. With this method it is possible to relate details in the time domain voltages and currents to corresponding variations in carrier densities, electrical field, etc. in the device. We have utilised the standard device simulator Medici, directly driven by sine voltage sources on both input and output. The resulting data from the simulations was then analysed using Matlab. Several 4H-SiC MESFET structures were evaluated by this technique and we found the p-type buffer layer doping and thickness to be crucial to obtain an optimum RF power. A 4H-SiC MESFET structure was found to have an output power of 6.2 W/mm at 1 GHz.

A numerical comparison between MOS control and junction control high voltage devices in SiC technology

A comprehensive numerical comparison between MOS control (MOSFETs) and junction control (JFETs) devices in SiC technology is presented. The study is carried out using the MEDICI device simulator and covers an interval of blocking voltages ranging from 600 V to 6.5 kV. The gate oxide failure phenomenon in SiC trench MOSFETs is studied and the effect of wide trenches and rounded trench corners on the voltage blocking performance is investigated. The paper continues with a comparative study of SiC MOSFETs and SiC JFETs. The JFET chosen has a particular channel geometry featuring a highly doped buffer layer to reduce the on-state resistance. The influence of the buffer layer and the gate voltage on the JFET on-state/breakdown performance is carefully investigated. The study concludes with a mixed-mode simulation of the transient behaviour of a 1.2 kV SiC JFET–Silicon MOSFET pair in a CASCODE configuration as a viable alternative to a single switch (either SiC MOSFET or JFET).

High Ge content photodetectors on thin SiGe buffers

PIN SiGe photodetectors (PD) are grown by MBE with Ge contents x=0, 0.10, 0.2, 0.27 and 0.5. For PDs with high Ge content, which are grown beyond the SiGe layer critical thickness, thin (sub 100 nm) strain relaxed, p +(B)-doped SiGe buffers are of special importance. The layer structure of the samples consists of a 5×10 18 cm −3 p +(B)-doped buffer layer as a bottom contact, followed by a 300 nm intrinsic active zone covered with a 3×10 20 cm −3 n ++(Sb)-doped top contact layer. Extremely low temperatures (LT) during the first growth stage of the SiGe buffers are implemented. Process windows for high strain relaxation on different substrates are determined. The role of growth conditions in crystal structure formation is in situ monitored by time resolved reflectivity (TRR) measurements. For comparison, pseudomorphic PDs and that on conventional graded buffers were also realised. Secondary ion mass spectrometry (SIMS), μ-Raman-spectroscopy and energy dispersive X-ray (EDX) analysis are performed to measure Ge content, composition profiles and degree of relaxation. The microstructure is characterised by cross-section transmission electron microscopy (XTEM). By optical microscopy with Nomarski differential interference contrast (NIC) combined with defect etching technique, typical defects in the layers were studied. Electrical measurements are performed to determine the different current components. The DC current–voltage characteristics show a distinct diode ‘s behaviour of the detectors, which are optically characterised in terms of reverse current for different incident wavelengths.

Growth and characterization of graded AlGaN conducting buffer layers on n + SiC substrates

GaN films on top of doped, graded AlGaN conducting buffer layers were grown by metal-organic chemical vapor deposition on n + SiC substrates. The effect of initial AlGaN composition and buffer layer doping level on the structural and morphological properties of these films and the conduction between these films and the substrate was investigated. A minimum resistance of 2 Ω was measured for vertical test structures.

Progress in the use of 4H-SiC semi-insulating wafers for microwave power MESFETs

The use of Silicon Carbide semi-insulating wafers has to be mastered in order to reach output power densities up to 3–4 W mm −1 in the 1–2 GHz frequency range (values that are currently targeted). This study shows that the buffer layer doping level and thickness have a great influence on the MESFET behavior. We have studied three epilayer configuration on SI substrates that differ only by the buffer layer. On two of them, a slow drain current decrease in d.c. mode was observed. On the third one, no d.c. current drift was observed without rf input power, but drain current decreases instantaneously when rf input power is switched on. Traps, located either in the buffer layer or in the substrate are supposed to be responsible for these drift phenomena. Load–pull measurements were performed at 2 GHz on transistors fabricated on the three different structures. One of them, with a 2 mm gate periphery, has been measured under 72 V drain–source bias voltage and 2.1 W mm −1 power density was obtained at 2 GHz. We believe these results are the first to be published on a SiC MESFET with d.c. bias voltage over 70 V.

Principle of operation and carrier distributions of AlGaAs/GaAs in-plane-gated channels

In-plane-gate field-effect transistors were fabricated on a modulation-doped AlGaAs/GaAs heterostructure substrate using focused ion beam implantation. The two-dimensional electron gas was divided up by insulating lines so as to define a coplanar gate and channel. The devices were simulated in two-dimensional cross section including the effects of fringing fields, surface states, and unintentional p-type doping in the nominally undoped GaAs buffer layer. Excellent agreement was obtained between measured and simulated channel conductance as a function of gate bias. The distribution of electrons in the channel was then studied as a function of gate bias. Simulations show that the two-dimensional electron gas in the channel is depleted through a combination of reduction in overall carrier density and effective width. The nonlateral depletion is enhanced by parasitic backgate coupling through the unintentionally doped buffer layer.

Reproducible growth of InAs xSb 1− x/InSb strained-layer superlattice photodiodes by low pressure MOCVD

Reproducible growth of InAs x Sb 1− x /InSb strained-layer superlattice photodiodes by low pressure metalorganic chemical vapor deposition (MOCVD) has resulted from the use of Zn doped InAs x Sb 1− x step-graded buffer layers. These photodiodes show improved performance with response to 10 μm and detectivities of 4 × 10 9 cm Hz 1 2 /W at 6 μm. Dislocation formation in InAs x Sb 1− x buffer layers grown on InSb substrates by MOCVD is shown to be reproducibly enhanced by p-type doping at levels exceeding the intrinsic carrier concentration at 475°C using diethylzinc. Carrier concentrations up to 6 × 10 18 cm -3 were obtained. The Zn doped buffer layers have proven to be reproducibly crack free for InAs x Sb 1− x step graded buffer layers with a final composition of x=0.12 lattice matched to a strained layer superlattice (SLS) with an average composition of x=0.09.

In situ monitoring and Hall measurements of GaN grown with GaN buffer layers

High-quality gallium nitride (GaN) film was obtained using a GaN buffer layer on a sapphire substrate. Using low-temperature Hall measurements, we obtained a maximum mobility about 3000 cm2/V s, at around 70 K. This mobility value is the highest reported, to our knowledge, for GaN films. The infrared radiation transmission intensity oscillations, which were caused by interference effects, were observed by means of an infrared radiation thermometer during GaN growth. The growth process of GaN film with GaN buffer layers was almost the same as that of GaN film with AlN buffer layers except when the thickness of GaN buffer layers was small. When the thickness of GaN buffer layers was small, an additional new growth process, in which the surface of GaN film became rough during the growth, was observed. The GaN growth with GaN buffer layers had a tendency to improve the surface morphology even if it became poor due to excess Si doping or low buffer layer thickness.