Abstract
The use of Silicon Carbide semi-insulating wafers has to be mastered in order to reach output power densities up to 3–4 W mm −1 in the 1–2 GHz frequency range (values that are currently targeted). This study shows that the buffer layer doping level and thickness have a great influence on the MESFET behavior. We have studied three epilayer configuration on SI substrates that differ only by the buffer layer. On two of them, a slow drain current decrease in d.c. mode was observed. On the third one, no d.c. current drift was observed without rf input power, but drain current decreases instantaneously when rf input power is switched on. Traps, located either in the buffer layer or in the substrate are supposed to be responsible for these drift phenomena. Load–pull measurements were performed at 2 GHz on transistors fabricated on the three different structures. One of them, with a 2 mm gate periphery, has been measured under 72 V drain–source bias voltage and 2.1 W mm −1 power density was obtained at 2 GHz. We believe these results are the first to be published on a SiC MESFET with d.c. bias voltage over 70 V.
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