Abstract
A comprehensive numerical comparison between MOS control (MOSFETs) and junction control (JFETs) devices in SiC technology is presented. The study is carried out using the MEDICI device simulator and covers an interval of blocking voltages ranging from 600 V to 6.5 kV. The gate oxide failure phenomenon in SiC trench MOSFETs is studied and the effect of wide trenches and rounded trench corners on the voltage blocking performance is investigated. The paper continues with a comparative study of SiC MOSFETs and SiC JFETs. The JFET chosen has a particular channel geometry featuring a highly doped buffer layer to reduce the on-state resistance. The influence of the buffer layer and the gate voltage on the JFET on-state/breakdown performance is carefully investigated. The study concludes with a mixed-mode simulation of the transient behaviour of a 1.2 kV SiC JFET–Silicon MOSFET pair in a CASCODE configuration as a viable alternative to a single switch (either SiC MOSFET or JFET).
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