Performance of SiC cascode JFETs under single and repetitive avalanche pulses

Abstract

In this paper, we investigate the single and repetitive avalanche performance and characteristics of different SiC device technologies including SiC cascode JFETs and SiC Trench MOSFETs. SiC Cascode JFETs exhibit a different failure mode from SiC MOSFETs due to the interaction between the low-voltage (LV) silicon MOSFET and the high-voltage (HV) SiC JFET through the resistance connecting the MOSFET source to the JFET gate. MOSFETs fail in avalanche typically due to parasitic BJT latch-up and/or thermal hot-spotting leading to a source-to-drain short. However, cascode JFETs can fail with the low voltage MOSFET still functional and a low resistance measured between the cascode terminals. The failure point of SiC Cascode JFETs in avalanche is therefore not clearly identifiable and the failure criteria will have to be reassessed. Measurements and simulations show that the connection between the JFET gate and the MOSFET source influences the avalanche duration and avalanche power. Finite element simulations show that increased leakage through the gate resistance of the SiC JFET at higher temperatures causes delayed transients in the VDS turn-OFF. Hence, the result is low-voltage avalanche turn-OFF where only the LV silicon MOSFET goes into avalanche and the JFET goes into linear mode. SiC Cascode JFETs show reduced performance under repetitive avalanche due to degradation of the JFET gate resistance and increased linear mode conduction of the SiC JFET. Failure analysis proves that the low voltage silicon MOSFET is unaffected while the avalanche current flows through the SiC JFET gate which appears to be shorted.