Dopant Segregation Technique Research Articles

NiSi/p⁺-Si(n⁺-Si)/n-Si(p-Si) Diodes With Dopant Segregation (DS): p-n or Schottky Junctions?

Dopant segregation (DS) technique has been extensively employed to tune Schottky barrier heights (SBHs) of NiSi/Si diodes, either leading to reduced specific contact resistivity ( $\rho _{\text {c}}$ ) in source/drain (S/D) Ohmic contacts, or enhanced current drivability in Schottky barrier S/D MOSFET (SB-MOSFET) where metallic NiSi is employed as S/D. A capacitance–voltage ( ${C}$ – ${V}$ ) method is usually adopted to reliably extract the SBHs of NiSi/Si for investigating the effectiveness of such a DS technique. In order to avoid large reverse leakage current which rules out the possibility of SBHs extraction during ${C}$ – ${V}$ measurements, dopants with opposite polarity to that in epitaxial Si substrate segregate at the NiSi/Si interface, for instance, boron DS (B DS) for NiSi/n-Si and arsenic DS (As DS) for NiSi/p-Si. This, however, raises one critical question, i.e., NiSi/p+-Si (B DS)/n-Si and NiSi/n+-Si (As DS)/p-Si are p-n or Schottky junctions. In this work, a dedicated circuit is devised to distinguish the type of as-fabricated NiSi/Si diodes with DS based on different switching mechanisms between p-n and Schottky junctions.

Analysis of a Schottky Barrier MOSFET for Synaptic Device Using Hot Carrier Injection

In this paper, we analyze the hot carrier injection (HCI) in an asymmetric dual-gate structure with a metallic source/drain. We propose a program/erase scheme where HCI occurs on the source side of the body. Owing to the large resistance of the Schottky barrier used, a large electric field is formed around the Schottky barrier. Therefore, impact ionization occurs as the gate voltage is increased and hot carriers are injected into the source side, which is less influenced by the drain voltage. We also analyze the program and erase efficiency by adjusting the Schottky barrier height or by using dopant segregation technique. We expect a small amount of current to flow and great efficiency of the program/erase operations to use as a synaptic device.

Formation of Ohmic Contacts to n-Type 4H-SiC at Low Annealing Temperatures

The formation of Ohmic contacts to n-type 4H-SiC layers at low annealing temperature using dopant segregation technique is reported. n-SiC epilayer was implanted with phosphorous and subsequently activated at 1700 °C. Ni metal contacts fabricated on phosphorous implanted and annealed epilayers produced Ohmic contacts with a specific contact resistivity (ρc) of ~7.2x10-5 Ω.cm2 at an annealing temperature of 550 °C. ρc decreased with further annealing temperature reaching a value of ~2.1x10-5 Ω.cm2 at 1000 °C. XRD analysis showed that nickel silicide phase was formed at both 550 °C and 1000 °C.

A Modified Scheme to Reduce the Specific Contact Resistivity of NiSi/Si Contacts by Means of Dopant Segregation Technique

In this work, a proposed modified scheme to reduce the specific contact resistivity (ρc) of NiSi/Si contacts by means of dopant segregation (DS) technique is presented. In contrast to conventional scheme in which NiSi is formed at 500°C/30s followed by B or As implantation and subsequently drive-in anneals to induce DS at the NiSi/Si interface, this modified scheme consists of the following steps: (1) Deposited Ni films undergo a rapid thermal anneal (RTA1) at a low temperature 300°C/60 s to form Ni-rich silicide i.e. Ni2Si instead of NiSi followed by the removal of un-reacted Ni; (2) implant boron (B) or arsenic (As) into pre-formed Ni-rich silicide and perform RTA2 at 500–700°C/30 s to transform Ni-rich silicide to NiSi as well as to induce DS at the NiSi/Si interface. For NiSi/n- and p-Si contacts, the ρc values at 600°C drive-in anneal temperature is reduced from 6.5 × 10−9 Ω-cm2 and 1.3 × 10−7 Ω-cm2 using conventional scheme to 5.1 × 10−9 Ω-cm2 and 1.0 × 10−7 Ω-cm2 using modified scheme respectively, with the presence of As or B DS. Enhanced DS at the NiSi/Si interface accounts for improved ρc in the modified scheme. This proposed modified scheme can be also applied to reduce the ρc values in the state-of-the-art NiGe/Ge contacts.

Schottky Barrier Height Tuning via the Dopant Segregation Technique through Low-Temperature Microwave Annealing.

The Schottky junction source/drain structure has great potential to replace the traditional p/n junction source/drain structure of the future ultra-scaled metal-oxide-semiconductor field effect transistors (MOSFETs), as it can form ultimately shallow junctions. However, the effective Schottky barrier height (SBH) of the Schottky junction needs to be tuned to be lower than 100 meV in order to obtain a high driving current. In this paper, microwave annealing is employed to modify the effective SBH of NiSi on Si via boron or arsenic dopant segregation. The barrier height decreased from 0.4–0.7 eV to 0.2–0.1 eV for both conduction polarities by annealing below 400 °C. Compared with the required temperature in traditional rapid thermal annealing, the temperature demanded in microwave annealing is ~60 °C lower, and the mechanisms of this observation are briefly discussed. Microwave annealing is hence of high interest to future semiconductor processing owing to its unique capability of forming the metal/semiconductor contact at a remarkably lower temperature.

A study on NiGe-contacted Ge n+/p Ge shallow junction prepared by dopant segregation technique

In this work, the effect of dopant segregation on the NiGe/n-Ge contact is studied by experiments and first-principles calculations. Both Al-contacted and NiGe-contacted n+/p junctions were fabricated. Phosphorus and arsenic ions were Implanted Before Germanide (IBG) formation or Implanted After Germanide (IAG) formation. The NiGe-contacted junction always exhibit higher forward current than the Al-contacted junction due to dopant segregation. First principles calculations predict that phosphorus atoms tend to segregate on both NiGe side and Ge side while arsenic atoms tend to segregate at Ge side. Since phosphorus has higher activation level and lower diffusion coefficient than arsenic, we propose a phosphorus IBG+arsenic IAG process. Shallow n+/p junction with junction depth 90nm below the NiGe/Ge interface is achieved. The lowest and average contact resistivity is 2×10−6Ωcm2 and 6.7×10−6Ωcm2, respectively. Methods which can further reduce the junction depth and contact resistivity are suggested.

Dopant-Segregation Technique for Leakage Reduction and Performance Improvement in Trigate Transistors Without Raised Source/Drain Epitaxy

A dopant-segregation technique for junction engineering has been demonstrated on trigate transistors using a process flow that does not include raised source/drain epitaxy. It is shown that the dopant-segregation technique reduces the OFF-state leakage current and improves the ON-state performance for NFET devices when compared with control devices built using conventional junction engineering. The dopant-segregation process has no observable impact on PFET device performance.

A modified scheme to tune the Schottky Barrier Height of NiSi by means of dopant segregation technique

A modified scheme to tune the Schottky Barrier Height (SBH) of NiSi effectively by means of dopant segregation (DS) technique is presented. This scheme consists of the following steps: (1) The deposited Ni films undergo a rapid thermal anneal (RTA1) at 300 °C/60 s to form Ni-rich silicide followed by removal of un-reacted Ni; (2) implant boron (B) or arsenic (As) into pre-formed Ni-rich silicide and RTA2 at 450–700 °C/30 s to transform Ni-rich silicide to NiSi and to induce DS at NiSi/Si interface as well. The SBHs to electrons (ϕbn) or to holes (ϕbp) of NiSi tuned using this scheme by B or As DS is ≥1.0 eV, corresponding to ϕbp or ϕbn ≤0.1 eV, comparable to those tuned using conventional scheme by DS, in which B or As ions are implanted into NiSi followed by drive-in anneals to induce DS at NiSi/Si interface.

(Invited) Ultrathin Ni1-xPtx Films as Electrical Contact in CMOS Devices

Metal silicide films are likely to continue their function as electrical contact in CMOS devices beyond the 22-nm technology node. For such devices, the thickness of the silicide films is projected in the technology roadmap to be below 10 nm. Nickelbased silicides are among the most competitive choices for this application. For this family of silicides, the latest experimental investigations show that upon identical formation conditions (temperature and time), the phase, crystallinity, morphological stability, and thickness of resultant silicide films sensitively depend on the thickness and composition of initially deposited Ni1-xPtx layers. A proper understanding of these experimental observations is instrumental to design and control of ultrathin Ni1-xPtx silicide films with desired properties. In order to achieve low-resistivity electrical contact to Si, dopant segregation technique can be combined with SADS(silicide as diffusion source) processing to modify the Schottky barrier height between the silicide films and the underlying Si.

CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing

We present a vertical-silicon-nanowire-based p-type tunneling field-effect transistor (TFET) using CMOS-compatible process flow. Following our recently reported n-TFET , a low-temperature dopant segregation technique was employed on the source side to achieve steep dopant gradient, leading to excellent tunneling performance. The fabricated p-TFET devices demonstrate a subthreshold swing (SS) of 30 mV/decade averaged over a decade of drain current and an Ion/Ioff ratio of >; 105. Moreover, an SS of 50 mV/decade is maintained for three orders of drain current. This demonstration completes the complementary pair of TFETs to implement CMOS-like circuits.

Analysis of Transconductance $(g_{m})$ in Schottky-Barrier MOSFETs

This paper experimentally investigates the unique behavior of transconductance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> ) in the Schottky-barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When the Schottky-barrier height (SBH) or a scaling parameter is not properly optimized, a peculiar shape of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> is observed. Thus, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> can be used as a novel metric that exhibits the transition of the carrier injection mechanisms from a thermionic emission (TE) to thermally assisted tunneling (TU) in the SB-MOSFETs. When the local maximum point of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> is observed, it can be expected that an incomplete transition occurs between TE and TU in SB-MOSFETs. When a dopant-segregation (DS) technique is implemented in the SB-MOSFETs, however, the carrier injection efficiency from the source to the channel is significantly improved, although the SBH is not minimized. As a consequence, the peculiar shape of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> disappears, i.e., a complete transition from TE to TU can be enabled by the DS technique.

Dopant-segregated Schottky barrier MOSFETs with an insulated dielectric oxide

An insulated dielectric oxide (IDO) is presented for the dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to suppress the unwanted on- and off-state leakage currents in short-channel DS-SBMOS. The effects of the IDO on DS-SBMOS are investigated using two-dimensional device simulations. Although the dopant segregation technique can efficiently modify a Schottky barrier to improve Schottky barrier MOSFETs, the performance of scaled DS-SBMOS suffers from degraded short-channel behavior and ambipolar conduction from the extension of a heavily doped segregation layer. With sidewall IDO insulators between the heavily doped N+ segregation layer and P+ halo region, band-to-band and ambipolar leakage currents are simultaneously minimized. Thus, an optimal halo can be utilized to control the short-channel effect without any constraints in problematic leakage currents. Using the IDO architecture, DS-SBMOS can be successfully scaled as a promising candidate for next-generation CMOS devices.

High-Performance Polycrystalline Silicon TFT on the Structure of a Dopant-Segregated Schottky-Barrier Source/Drain

A high-performance polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Schottky-barrier (SB) source/drain (S/D) junctions is proposed. A p-channel operation on the intrinsic nickel (Ni) silicided S/D was successfully realized with the aid of a thin active layer, despite the fact that the Ni silicided material shows a high SB height (SBH) for holes. Furthermore, for n-channel operation, the dopant-segregation technique implemented on the intrinsic Ni silicide was utilized to reduce the effective SBH for electrons. The results show a higher on-current due to the lower parasitic resistance as well as superior immunity against short-channel effects, compared to the conventional poly-Si TFT composed of p-n S/D junctions.

Schottky Barrier Height Modulation of Nickel Germanide Schottky Diodes by the Germanidation-Induced Dopant Segregation Technique

Modulation of Schottky barrier height (SBH) is successfully demonstrated by a germanidation-induced dopant segregation technique. The barrier height of NiGe/Ge Schottky diodes is modulated by 0.06−0.15eV depending on annealing temperature. The results show the change of SBH is not attributed to the phase change of nickel germanides but to dopant segregation at the interface of germanides/germanium which causes the upward conduction energy band. In addition, we first observe a Raman peak at about 217 cm−1 corresponding to NiGe, which has not been reported till now. The surface morphology of nickel germanides can be improved by BF2 implantation before germanidation. The results may provide guidelines for the design of Schottky source/drain germanium-based devices.

Application of dopant segregation to metal-germanium-metal photodetectors and its dark current suppression mechanism

We report the mechanism of dopant-segregation (DS) technique as applied in metal-germanium-metal photodetectors (MGM-PDs) for dark current suppression. Photodetectors with various dopant-segregation strategies were designed, fabricated, and characterized. Results show that asymmetric MGM-PD, with n- and p-type dopants segregated separately in two NiGe electrodes, is the optimized scheme in terms of dark current and responsivity. It shows a dark current of 10−6A at −1V, which is two to three orders of magnitude lower than that of MGM-PD without DS. n-type dopant (As) segregation in NiGe barrier increases the hole Schottky barrier height to 0.5eV and, thus, plays a crucial role in dark current suppression.

Dark-Current Suppression in Metal–Germanium–Metal Photodetectors Through Dopant-Segregation in NiGe—Schottky Barrier

We demonstrate, for the first time, the application of dopant-segregation (DS) technique in metal-germanium- metal photodetectors for dark-current suppression and high-speed performance. Low defect density and surface smooth epi-Ge (~300 nm) layer was selectively grown on patterned Si substrate using two-step epi-growth at 400degC/600degC combined with a thin (~10 nm) low-temperature Si/Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> buffer layer. NiGe with DS effectively modulates the Schottky barrier height and suppresses dark current to ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A at -1 V bias (width/spacing: 30/2.5 mum). Under normal incidence illumination at 1.55 mum, the devices show photoresponsivity of 0.12 A/W. The 3 dB bandwidth under - 1 V bias is up to 6 GHz.

Dopant segregation in SOI Schottky-barrier MOSFETs

We present experimental results on silicon-on-insulator Schottky-barrier MOSFETs with fully silicided NiSi source and drain contacts. Dopant segregation during silicidation was used to improve the device characteristics: on-currents, significantly higher than without dopant segregation as well as an almost ideal off-state are demonstrated in n-type as well as p-type SB-MOSFETs. Temperature dependent measurements show that the effective Schottky-barrier height in devices with segregation can be strongly lowered. In addition, we investigate the dopant segregation technique with simulations. Comparing simulations with experiments it turns out that the spatial extend of the segregation layer is on the few nanometer scale which is necessary for ultimately scaled devices. Furthermore, the use of ultrathin-body SOI in combination with ultrathin gate oxides results in an even further increased transmission through the Schottky barriers and consequently leads to strongly improved device characteristics. As a result, the dopant segregation technique greatly relaxes the requirement of low Schottky-barrier silicides for high performance transistor devices.

Impact of dopant segregation on fully depleted Schottky-barrier SOI-MOSFETs

The effect of silicidation induced dopant segregation (DS) on the electrical behavior of silicon-on-insulator Schottky-barrier MOSFETs (SB-MOSFETs) is investigated. We use ion implantation with arsenic and boron and subsequent nickel silicidation to create highly n- and p-doped layers at the contact-channel interfaces. Devices with dopant segregation exhibit an inverse subthreshold slope of ∼60 mV/dec and improved on-currents for n-type as well as p-type SB-MOSFETs due to a lowering of the effective Schottky-barrier height (SBH) compared to SB-MOSFETs without DS. In addition, our findings are supported by simulations. Temperature dependent measurements show that a reduced SBH as low as ∼0.1 eV for electrons has been achieved. As a result, the dopant segregation technique greatly relaxes the requirement for low SB silicides to realize high performance SB-MOSFET devices.