Domino Logic Circuits Research Articles

Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipa- tion than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power super- threshold computing scheme is proposed to reduce power dissipations of FinFET Domino logic circuits. The pull-down transistors of all FinFET Domino circuits are configured in parallel, and thus improve operating speed. Unlike near- threshold circuits, super-threshold ones are supplied by much a larger supply voltage than the threshold voltage, but it is lower than the standard supply voltage. Super-threshold FinFET logic circuits can attain low power consumption with fa- vorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS ones. The basic Domino logic gates are compared with static logic ones in terms of en- ergy consumption, delay, energy delay product (EDP), and maximum operation frequency with different voltages from near-threshold to super-threshold regions. All circuits are simulated with HSPICE at a PTM (Predictive Technology Mod- el) 32nm FinFET technology. The results show that the Domino gates can operate faster than static ones. In addition, it is also shown that Domino gates exhibit the best EDP in super-threshold regions (about 700mV). Compared with the stand- ard supply voltage of 1.0 V, the Domino gates supplied by 0.8V can attain energy reductions of more than 38.3% with a small performance penalty of about 14%.

English

In recent years power saving is one of the important thing. Domino logic circuit is power efficient cicuit,so it is widely used in variety of applications in digital design. But it has a limitation of low noise immunity and more leakage current. This problem can be solved by using keeper transistor to compensate leakage current of pull down network. The conventional keeper domino circuit reduces the performance and more power consumption due to the contention between keeper transistor and pull down network. This problem is more in wide fan in gates due to large number of leaky paths connected to the dynamic node. In this paper ,a new technique is proposed which overcomes the contention problem and reduces power dissipation and provide high noise immunity. Simulations of wide fan in gates are designed using TSMC 180nm technology with Vdd=1V at 27°c and 110°c using mentor graphics.

Performance Analysis of High Speed Domino CMOS Logic Circuits

the demand of low power high performance arithmetic circuits multiplies, during this paper, we aim to introduce a style of latest MT-CMOS domino logic and FTL dynamic logic technique to style adder circuit. The MT-MOS transistors cut back the facility dissipation by minimizing sub threshold run current in the introduced domino logic circuits. The MT-NMOS semiconductor connected in discharging path of output electrical converter may be applied for pipeline structure to scale back the facility consumptions and increase fan-out. Dynamic logic vogue CMOS circuit is employed to enhance the speed and cut back the world of style by decreasing the device count. The introduced FTL dynamic logic circuit improves the performance by evaluating the computational blocks partially before its input signals are formalized and then rapidly perform a final evaluation as soon as the inputs arrive. This dynamic logic formation is like minded for an arithmetic circuit wherever the important path s created of an outsized cascade of inverting gates is created. The mixture of MT-CMOS and dynamic logic circuit provides high fan-out, high change frequencies with each lower delay and dynamic power consumption. The simulation results of those projected low power high performance circuits provide 75% power reduction, three times redoubled high speed operation and active space reduction, whereas revealing lower sensitivity to power provide, temperature, electrical phenomenon load and method variations than the dynamic domino CMOS technologies.

Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

Domino logic is a CMOS-based evolution of the dynamic logic techniques  based on either PMOS or NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

Performance of low power Domino Circuits using pseudo dynamic buffer

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit for different logic function, loading condition, clock frequency and power supply. Our proposed circuit reduces power consumption and power delay product of the domino circuit as compare to other domino circuit proposed earlier. All the simulation result is carried out TSMC -0.18μm CMOS technology at 1.8V power supply.

A low-leakage and NBTI-mitigated N-type domino logic

NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDD, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.

Domino Logic Topologies of OR Gate with Variable Threshold Voltage Keeper

In this paper, we tend to take four domino circuit topologies to boost the strength and lower the consumption of power. A high speed and noise immune domino logic circuit is given that uses the property of the footer semiconductor to raise the sensitivity of the dynamic node to noise and eventually in improved performance. Dynamic logic circuits are used for prime performance and high speed applications. We tend to analyze and compare completely different domino logic style topologies for lowering the sub-threshold outpouring current in standby mode NMOS block , increasing the speed and increasing the noise immunity. We tend to compare power, delay, and Power Delay Product (PDP) of various topologies. Simulation is finished employing a 45nm cadence tool for eight input OR circuit. Our projected circuits scale back power consumption by 100 percent to 35 the troubles, improvement of unity noise gain of 39% to 85% and have a higher figure of advantage as compared to conditional keeper domino. The simulation results unconcealed that prime Speed Conditional keeper Domino (CKD) circuit offers the most effective ends up in terms of reduction in delay and power consumption as compared to different circuits.

A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting.

Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits

Leakage power consumption is a major technical problem faced in nanometer or deep submicron CMOS circuit technology. A new circuit technique based on “lector stacking” is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in the idle and non-idle modes of operation for domino circuits. In this technique a p-type and an n-type leakage control transistor (LCT) are introduced between the pull-up and pull-down network, and the gate of one is controlled by the source of the other. For any combination of inputs, one of the LCTs will operate near its cut-off region and will increase the resistance between supply voltage and ground, resulting in reduced leakage current. Lector stacking retains the logic state during the idle mode as in the conventional footerless domino logic. Furthermore, the leakage current is suppressed at the output inverter circuit by adding a diode-footed transistor below the n-type transistor of the inverter, offering a more resistive path between supply voltage and ground.The proposed circuit technique for AND2, OR2, OR4, and OR8 circuits reduces the active power consumption by 13.66 % to 44.45 % and by 12 % to 33 % at the low and high die temperatures, respectively, compared to the standard footerless domino logic circuits. During idle mode for the same logic gates, 1.64 % to 79.39 % and 1.2 % to 35.19 % reduction of leakage current is observed with low and high inputs at 25 °C and 110 °C respectively. Similarly, during non-idle mode 0.94 % to 99.3 % and 1.57 % to 98.58 % is observed with low and high inputs at 25 to 110 °C, respectively, when compared to standard footerless domino logic circuits.

A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits

A new dual-threshold circuit technique is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 34% to 57.5% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25 0 C and 110 0 C temperatures the maximum leakage power saving of 99.97% is achieved when compared to standard dual-threshold domino logic circuits in a 65nm CMOS technology.

A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits

A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25℃ and 110℃ temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.

Domino logic designs for high-performance and leakage-tolerant applications

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.

Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS

Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. This paper provides comprehensive analyses on the impacts of NBTI and PBTI on wide fan-in domino gates with high-k metal-gate devices. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG) are analyzed in the presence of NBTI/PBTI degradation. It has been shown that the main concern is the degradation impact on delay which can increase up to 16.2% in a lifetime of 3years. We have also proposed a degradation tolerant technique to compensate for the NBTI/PBTI-induced delay degradation in domino gates with a negligible impact on UNG and power.

Lower-power TSPC-based Domino Logic Circuit Design with 2/3 Clock Load

In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit design. Compared to using three clock transistors in the conventional TSPC-based scheme, the proposed circuit only requires two transistors. As a result, the clock load capacitance is reduced, leading to low power consumption in the clock distribution network. A keeper design to solve charge sharing is also demonstrated. Simulation results using 90nm and 45nm CMOS technologies are provided and iscussed, respectively, which illustrate power saving as compared to conventional design not only when the input logic is active but also when the input logic is held to zero.

Low power dynamic logic circuit design using a pseudo dynamic buffer

In this paper, we propose a pseudo dynamic buffer (PDB) for footed domino logic circuit implementation. Using the proposed PDB structure, the output pulse during the precharge process is prevented from propagating to the output stage, as is the case in conventional case. As a result, up to half of the power is saved compared to a conventional domino gate, while improving the sampling window of the dynamic gate. This PDB structure is applicable not only for Pull-down network (N-type) dynamic logic, but also for Pull-up networks (P-type). Simulation results illustrate improved performance using the proposed scheme compared to the conventional dynamic logic for different loading conditions, clock frequencies and logic functions. In addition, our proposed design reduces the clock loading from conventional three to two transistors. As a result, the proposed scheme significantly saves power due to lower load capacitance on the clock bus. Test structures are fabricated in 0.35μm CMOS technology. Measurement results validate the proposed concept and illustrate power saving as compared to conventional design.

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Negative Bias Temperature Instability (NBTI) in pMOS transistors has become a major reliability concern in the state-of-the art digital circuit design. This paper discusses the effects of NBTI on 32nm technology high fan-in dynamic OR gate, which is widely used in high-performance circuits. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG), are analyzed in the presence of NBTI degradation. We have shown the degradation in the output inverter pMOS transistor of the domino gate has a dominant impact on the delay in comparison with the keeper impact. Based on this analysis we have proposed that upsizing just the output inverter pMOS transistor can compensate for the NBTI degradation. Moreover, the impact of tuning the duty cycle of the clock has been investigated. It has been shown that although the keeper and the precharge transistors experience more NBTI degradation by increasing the low level in the clock signal, the total performance of the circuit will improve. We have also proposed an adaptive compensation technique based on Forward Body Biasing (FBB), to recover the performance of the aged circuit.

Power aware channel width tapering of serially connected MOSFETs

In this paper a new transistor channel width tapering scheme called Hill tapering for FET chains is proposed with specific emphasis on power dissipation and layout area of the tapered chains. This tapering scheme results in the lowest power dissipation and physical area compared to any of the existing tapering schemes like linear, exponential or optimal tapering. It also offers high speed operation. The proposed scheme is general and can be used in all domino logic circuit designs. SPICE simulation results have shown that up to 81% power dissipation reduction could be achieved by using the proposed tapering scheme.

Energy-Efficient, Noise-Tolerant CMOS Domino VLSI Circuits in VDSM Technology

Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in dynamic logic such as domino is often used in performance critical paths, to achieve high speeds where static CMOS fails to meet performance objectives. However, domino gates typically consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static CMOS gates. Keeping in view of the above stated problems in previous existing designs, novel energy- efficient domino circuit techniques are proposed. The proposed circuit techniques reduced the dynamic switching power consumption; short-circuit current overhead, idle mode leakage power consumption and enhanced evaluation speed and noise immunity in domino logic circuits. Also regarding performance, these techniques minimize the power-delay product (PDP) as compared to the standard full-swing circuits in deep sub micron CMOS technology. Also the noise immunity of the CMOS Domino circuits with various techniques and keepers are analyzed. Various noise sources are considered and noise immune domino logic is proposed.

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS

In this paper, the impact of negative bias temperature instability (NBTI) on dynamic logic circuits is analyzed and a design technique for a wide fan-in domino gate based on Genetic Algorithm (GA) optimization is proposed. In this technique, the degraded delay due to NBTI during the lifetime of the circuit is minimized subject to the constraints on area, power consumption and unity noise gain (UNG). The proposed optimization method is implemented in a 65-nm technology for a lifetime of 3 years. In comparison with a typical design, the optimized results show an improvement of more than 21.6% in delay during the circuit lifetime with a negligible change in the power and the UNG. The proposed method has the advantage that it can be used for any desired circuit lifetime with any reasonable constraints on design parameters, just with setting the corresponding parameters in the algorithm.

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS: errata

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS: errata