Abstract
A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25℃ and 110℃ temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.
Highlights
For high-speed chip performance domino circuits are employed and can be classified into footerless and footed domino [1,2,3]
We study the sources of leakage current in footerless domino and show that includes the following: Subthreshold leakage current (Isub) and Igate are functions of inputs applied and dependent on the clock signal state
BISM4 device model is used for simulating the standard footerless domino logic and proposed technique circuits for accurate estimation of subthreshold and gate oxide leakage currents
Summary
For high-speed chip performance domino circuits are employed and can be classified into footerless and footed domino [1,2,3]. High leakage current in nanometer regime becomes a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. On the other hand, when the well-to-source junction of a MOSFET is reverse biased, there is a body effect that increases the threshold voltage and decreases subthreshold leakage. Junction leakage that results from minority carrier diffusion and drift near the edge of depletion regions, and from generation of electron hole pairs in the depletion regions of reverse-bias junctions When both n regions and p regions are heavily doped, as is the case for some advanced MOSFETs, there is junction leakage due to band-to-band tunneling (BTBT) [6]. Punch through leakage, which occurs when there is decreased separation between depletion regions at the drain-substrate and the source-substrate junctions This occurs in short-channel devices, where this separation is relatively small.
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