Direct Memory Research Articles

Development of a wide-range and fast-response digitizing pulse signal acquisition and processing system for neutron flux monitoring on EAST

The neutron count rate fluctuation reaches six orders of magnitude between the ohmic plasma scenario and high power of auxiliary heating on an experimental advanced superconducting tokamak (EAST). The measurement result of neutron flux monitoring (NFM) is a significant feedback parameter related to the acquisition of radiation protection-related information and rapid fluctuations in neutron emission induced by plasma magnetohydrodynamic activity. Therefore, a wide range and high time resolution are required for the NFM system on EAST. To satisfy these requirements, a digital pulse signal acquisition and processing system with a wide dynamic range and fast response time was developed. The present study was conducted using a field-programmable gate array (FPGA) and peripheral component interconnect extension for instrument express (PXIe) platform. The digital dual measurement modes, which are composed of the pulse-counting mode and AC coupled square integral’s Campbelling mode, were designed to expand the measurement range of the signal acquisition and processing system. The time resolution of the signal acquisition and processing system was improved from 10 to 1 ms owing to utilizing high-speed analog-to-digital converters (ADCs), a high-speed PXIe communication with a direct memory access (DMA) mode, and online data preprocessing technology of FPGA. The signal acquisition and processing system was tested experimentally in the EAST radiation field. The test results showed that the time resolution of NFM was improved to 1 ms, and the dynamic range of the neutron counts rate was expanded to more than 10^{6} counts per second. The Campbelling mode was calibrated using a multipoint average linear fitting method; subsequently, the fitting coefficient reached 0.9911. Therefore, the newly developed pulse signal acquisition and processing system ensures that the NFM system meets the requirements of high-parameter experiments conducted on EAST more effectively.

A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration

Low-cost high-volume internet of things sensors require an end-to-end secure private-content exchange. Restricted energy and computing of system-on-a-chip for low-cost sensor applications drive lightweight hardware acceleration of security primitives. A trade-off between power and time needs to be achieved to develop such primitives. The main challenge is to handle memory transportation in the crypto-accelerator. Here we propose different approaches for AES-128/256 Sbox acceleration schemes. We designed a Sbox unit to be connected as a logic unit. The unit was tested as a RISC-V ISA instruction in the RISC-V processor to reduce software execution times. This unit was also included in an AES hardware core with direct memory access (DMA), which avoids using the main processor to access the data. We fabricated a RISC-V based 32-bit SoC in a standard 180nm CMOS technology that includes the Sbox calculation using pipeline and a pure-combinational approach. Measurement results indicate lower memory access and lower energy requirements than pure software approaches up to 100 times with a custom Sbox instruction. The AES core also provides a minimum energy consumption of 3.58 pJ/cycle. At its best, the combined SoC performs the encryption in active-mode with energy consumption of 9.7 pJ/bit. This solution offers up to three times energy savings compared to previously reported work.

Understanding I/O Direct Cache Access Performance for End Host Networking

Direct Cache Access (DCA) enables a network interface card (NIC) to load and store data directly on the processor cache, as conventional Direct Memory Access (DMA) is no longer suitable as the bridge between NIC and CPU in the era of 100 Gigabit Ethernet. As numerous I/O devices and cores compete for scarce cache resources, making the most of DCA for networking applications with varied objectives and constraints is a challenge, especially given the increasing complexity of modern cache hardware and I/O stacks. In this paper, we reverse engineer details of one commercial implementation of DCA, Intel's Data Direct I/O (DDIO), to explicate the importance of hardware-level investigation into DCA. Based on the learned knowledge of DCA and network I/O stacks, we (1) develop an analytical framework to predict the effectiveness of DCA (i.e., its hit rate) under certain hardware specifications, system configurations, and application properties; (2) measure penalties of the ineffective use of DCA (i.e., its miss penalty) to characterize its benefits; and (3) show that our reverse engineering, measurement, and model contribute to a deeper understanding of DCA, which in turn helps diagnose, optimize, and design end-host networking.

Amorphous Boron Nitride Memristive Device for High-Density Memory and Neuromorphic Computing Applications.

Although two-dimensional (2D) nanomaterials are promising candidates for use in memory and synaptic devices owing to their unique physical, chemical, and electrical properties, the process compatibility, synthetic reliability, and cost-effectiveness of 2D materials must be enhanced. In this context, amorphous boron nitride (a-BN) has emerged as a potential material for future 2D nanoelectronics. Therefore, we explored the use of a-BN for multilevel resistive switching (MRS) and synaptic learning applications by fabricating a complementary metal-oxide-semiconductor (CMOS)-compatible Ag/a-BN/Pt memory device. The redox-active Ag and boron vacancies enhance the mixed electrochemical metallization and valence change conduction mechanism. The synthesized a-BN switching layer was characterized using several analyses. The fabricated memory devices exhibited bipolar resistive switching with low set and reset voltages (+0.8 and -2 V, respectively) and a small operating voltage distribution. In addition, the switching voltages of the device were modeled using a time-series analysis, for which the Holt's exponential smoothing technique provided good modeling and prediction results. According to the analytical calculations, the fabricated Ag/a-BN/Pt device was found to be memristive, and its MRS ability was investigated by varying the compliance current. The multilevel states demonstrated a uniform resistance distribution with a high endurance of up to 104 direct current (DC) cycles and memory retention characteristics of over 106 s. Conductive atomic force microscopy was performed to clarify the resistive switching mechanism of the device, and the likely mixed electrochemical metallization and valence change mechanisms involved therein were discussed based on experimental results. The Ag/a-BN/Pt memristive devices mimicked potentiation/depression and spike-timing-dependent plasticity-based Hebbian-learning rules with a high pattern accuracy (90.8%) when implemented in neural network simulations.

An FPGA-Accelerated Parallel Digital Beamforming Core for Medical Ultrasound Sector Imaging.

Plane-wave transmission followed by parallel receive beamforming is popular among high frame rate (HFR) ultrasound (US) imaging methods. However, due to technological limitations, HFR imaging is not widely successful in clinical US. The proposed work aims to design a field-programmable gate array (FPGA)-accelerated parallel beamforming core for medical US sector imaging systems. This architecture supports up to 128 channels and forms 28 beams per plane wave transmission in parallel. A block random access memories (BRAMs)-based, 28-read one-write (28R1W) multi-ported delay line architecture is actualized to realize the delay line. In addition, to optimize the FPGA memory, the required beam focusing delays are stored in an external static random access memory (SRAM) and are loaded into the internal delay line registers by a cycle stealing direct memory access (DMA). The FPGA prototype validation and verification are performed on the custom-designed Xilinx-Kintex-7 XC7C410T FPGA-based US imaging platform. The results showed that for a field of view (FOV) of 90° with 0.5° resolution, 640×480 imaging size, a ft/s of 714 is achieved. The performance of the proposed parallel beamformer architecture is compared with existing development works and concluded that the architecture is superior due to its occupancy of FPGA hardware resources and the processing speed.

Publisher Correction: Subradiant directional memory in cooperative scattering

Publisher Correction: Subradiant directional memory in cooperative scattering

Asynchronous Wrapper-Based Low-Power GALS Structural QDMA

The design of System-on-Chip systems using synchronous circuits involves complex clock distribution strategies, which envisage challenges for designers to integrate large-scale systems. Globally Asynchronous Locally Synchronous architectures containing asynchronous port controllers encapsulated in the self-timed wrapper have been adopted in this work. These port controllers communicate through Asynchronous Finite State Machines defined by Signal Transition Graphs are implemented adopting the C element. This GALS architecture implemented for the point-to-point interface can also be modified for the multipoint interface. The proposed methodology uses a two-phase handshake protocol to communicate between two Locally Synchronous modules as it has fewer signal transitions, which, in turn, reduces latency. In this paper, the Queue Direct Memory Access subsystem is implemented using the Vivado simulator on UltraScale+™ device at a maximum frequency of 257.4MHz, and various parameters are reported. A comparison shows that the proposed wrapper has improved latency time of 53%, with a reduction in power dissipated by 27% and an increase in gate count by 13%.

Deep convolutional neural networks-based Hardware–Software on-chip system for computer vision application

Embedded vision systems are the best solutions for high-performance and lightning-fast inspection tasks. As everyday life evolves, it becomes almost imperative to harness artificial intelligence (AI) in vision applications that make these systems intelligent and able to make decisions close to or similar to humans. In this context, the AI’s integration on embedded systems poses many challenges, given that its performance depends on data volume and quality they assimilate to learn and improve. This returns to the energy consumption and cost constraints of the FPGA-SoC that have limited processing, memory, and communication capacity. Despite this, the AI algorithm implementation on embedded systems can drastically reduce energy consumption and processing times, while reducing the costs and risks associated with data transmission. Therefore, its efficiency and reliability always depend on the designed prototypes. Within this range, this work proposes two different designs for the Traffic Sign Recognition (TSR) application based on the convolutional neural network (CNN) model, followed by three implantations on PYNQ-Z1. Firstly, we propose to implement the CNN-based TSR application on the PYNQ-Z1 processor. Considering its runtime result of around 3.55 s, there is room for improvement using programmable logic (PL) and processing system (PS) in a hybrid architecture. Therefore, we propose a streaming architecture, in which the CNN layers will be accelerated to provide a hardware accelerator for each layer where direct memory access (DMA) interface is used. Thus, we noticed efficient power consumption, decreased hardware cost, and execution time optimization of 2.13 s, but, there was still room for design optimizations. Finally, we propose a second co-design, in which the CNN will be accelerated to be a single computation engine where BRAM interface is used. The implementation results prove that our proposed embedded TSR design achieves the best performances compared to the first proposed architectures, in terms of execution time of about 0.03 s, computation roof of about 36.6 GFLOPS, and bandwidth roof of about 3.2 GByte/s.

Subradiant directional memory in cooperative scattering

Subradiant directional memory in cooperative scattering

АНАЛІЗ ЗАГРОЗ БЕЗПЕКИ МІКРОКОНТРОЛЕРІВ

In the article the materials of individual studies of the main security problems in microcontrollers operating as part of control systems of both general and specialized devices were considered and analyzed. In particular, the main trends of security threats were analyzed and the main attacks vectors were presented. Foreign and domestic experience of manifestation of unauthorized influences and cyber threats in the main most critical places of microcontroller architecture is analyzed. The analysis showed that the basic places of security threats and interventions to the microcontroller are: registers, stack, LPA, memory (EEPROM and Flash), input-output ports, circuits and interfaces for data transfer to the MC, circuits for additional functionality for connecting to external peripheral devices and channels for connecting the clock oscillator. In addition, explorations were carried out on the main threats of the microcontroller system memory, namely: interference with direct memory access, access to control registers and access to the microcontroller buffer, buffer stack overflow, remote code execution, external access and attacks on secondary channels (including via external data lines in the MC), changing the order of addressing in the MC, changing / replacing the values of addresses and stack numbering, interfering with the work of data registers and indicating the state of the input / output ports of the microcontroller. A number of protection mechanisms for microcontrollers have also been studied, which together can reduce the risks of unauthorized actions on the microcontroller system. These include: cyclic code redundancy control, power monitoring and resource monitoring, the using of isolation and control of the functionality of the clock system, control of the integrity and reliability of the memory contents, control of external physical and electrical parameters of the microcontroller, virtualization of the main computing process and its multi-level redundancy and restoration of previous states, the using of cryptographic systems and data processing algorithms, the using of multi-level software and hardware isolation.

Exploring the role of context models in memory-building: the completion of informative voids and the re-organisation of narratives in second-hand memories

The transmission of memory after traumatic collective events (such as armed conflicts) always involves a discursive re-construction from a present viewpoint. In the case of new generations who have no direct memories of the conflict, a variety of contextual factors can interfere in the process of meaning-making. In this paper, we explore some of the discursive strategies employed by youngsters in order to fill in informational voids or to manage discourses that seem contradictory with their current context or pre-established belief systems when re-building narratives about violent conflicts in their community. Oral data collected from eight in-depth interviews with adolescents belonging to the first post-conflict generation in the Basque Country was analysed, combining theories from Memory Studies and theoretical-methodological approaches from Critical Discourse Analysis. Four types of rearrangement of information were identified during the interviews: all speakers drew on contextual information and pre-established mental models in order to fill in informational gaps, even if the resulting narratives sometimes altered the original meaning. Evidence suggests that remembering is a discursive practice strongly influenced by the current context and situation of the speaker, which would offer an explanation as to why collective memory changes with each generation.

Optimization of Multi-Core Accelerator Performance Based on Accurate Performance Estimation

Multicore accelerators have emerged to efficiently execute recent applications with complex computational dimensions. Compared to a single-core accelerator, a multicore accelerator handles a larger amount of communication and computation simultaneously. Since the conventional performance estimation algorithm tailored to single-core accelerators cannot estimate the performance of multicore accelerators accurately, we propose a novel performance estimation algorithm for a multicore accelerator. The proposed algorithm predicts a dynamic communication bandwidth of each direct memory access controller (DMAC) based on the runtime state of DMACs, making it possible to estimate the communication amounts handled by DMACs accurately by taking into account the temporal intervals. The proposed algorithm is evaluated for convolutional neural networks and wireless communications. The experimental results using a pre-register transfer level (RTL) simulator shows that the proposed algorithm can estimate the performance of a multicore accelerator with the estimation error of up to 2.8%, regardless of the system communication bandwidth. These results were also verified by the hardware implementations on Xilinx ZYNQ. In addition, the proposed algorithm is used to explore a design space of accelerator core dimensions, and the resulting optimal core dimension provides performance gains of 10.8% and 31.2%, compared to the conventional multicore accelerator and single-core accelerator, respectively. The source code is available on the GitHub repository: <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/SDL-KU/OptAccTile</uri> .

CloudChain: A Cloud Blockchain Using Shared Memory Consensus and RDMA

Blockchain technologies can enable secure computing environments among mistrusting parties. Permissioned blockchains are particularly enlightened by companies, enterprises, and government agencies due to their efficiency, customizability, and governance-friendly features. Obviously, seamlessly fusing blockchain and cloud computing can significantly benefit permissioned blockchains; nevertheless, most blockchains implemented on clouds are originally designed for loosely-coupled networks where nodes communicate asynchronously, failing to take advantages of the closely-coupled nature of cloud servers. In this paper, we propose an innovative cloud-oriented blockchain -- CloudChain, which is a modularized three-layer system composed of the network layer, consensus layer, and blockchain layer. CloudChain is based on a shared-memory model where nodes communicate synchronously by direct memory accesses. We realize the shared-memory model with the Remote Direct Memory Access technology, based on which we propose a shared-memory consensus algorithm to ensure presistence and liveness, the two crucial blockchain security properties countering Byzantine nodes. We also implement a CloudChain prototype based on a RoCEv2-based testbed to experimentally validate our design, and the results verify the feasibility and efficiency of CloudChain.

Розробка алгоритмів та програмного забезпечення систем вимірювання та аналізу вібрації

An analysis is presented in the field of vibration control, methods and algorithms for processing vibration data. The main existing problems of systems for diagnosing the state of equipment of complex structures are identified, directions for their solution are shown. The development of an algorithm and software for solving problems of vibration control with the determination of amplitude-phase parameters in real time and processing of vibration data to assess the technical condition of mechanisms is proposed. The results obtained form the theoretical and practical basis for the development of software for computer systems for solving problems of vibration control in real time, providing continuous recording and determination of amplitude-phase parameters. Features of the input of vibration data in vibration control systems make it possible to accurately determine the moment of their readiness, which, along with the organization of data transmission via a direct memory access channel and a special implementation of the input procedure, allows data to be received in real time. They can be used to modernize and further develop existing systems. The developed methods and algorithms for the analysis of vibration signals can be used in automated vibration control and decision support systems to determine the quality of manufacturing and assembly of various components, assess the residual resistance and rigidity, monitor and evaluate the state of mechanisms and assemblies with rotational motion. The proposed method for the formation of diagnostic features and the determination of informatively significant parameters for assessing the technical condition of complex mechanisms is based on the use of spectral analysis. Operational and multifunctional analysis of large volumes of experimental data will expand the functionality of vibration control systems.

A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

With the increasing popularity of the Internet of Things (IoT), the issue of its information security has drawn more and more attention. To overcome the resource constraint barrier for secure and reliable data transmission on the widely used IoT devices such as wireless sensor network (WSN) nodes, many researcher studies consider hardware acceleration of traditional cryptographic algorithms as one of the effective methods. Meanwhile, as one of the current research topics in the reduced instruction set computer (RISC), RISC-V provides a solid foundation for implementing domain-specific architecture (DSA). To this end, we propose an extended instruction scheme for the advanced encryption standard (AES) based on RISC-V custom instructions and present a coprocessor designed on the open-source core Hummingbird E203. The AES coprocessor uses direct memory access channels to achieve parallel data access and processing, which provides flexibility in memory space allocation and improves the efficiency of cryptographic components. Applications with embedded AES custom instructions running on an experimental prototype of the field-programmable gate array (FPGA) platform demonstrated a 25.3% to 37.9% improvement in running time over previous similar works when processing no less than 80 bytes of data. In addition, the application-specific integrated circuit (ASIC) experiments show that in most cases, the coprocessor only consumes up to 20% more power than the necessary AES operations.

Indirect stabilization of coupled abstract evolution equations with memory: Different propagation speeds

We consider the Cauchy problem for coupled second‐order evolution equations in a Hilbert space with indirect memory damping, which arises from the theory of viscoelasticity. Here, the coefficients of the main operators in the system are non‐equal (the case of different speeds of propagation). Under much weaker assumptions on memory kernels, we obtain a polynomial decay rate, whereas it is known that exponential stability does not hold. This work essentially generalizes and improves the related ones in the literature. As an application of our abstract results, we also establish for the Timoshenko system the so far best decay rate under such weak assumptions on the memory kernel in the case of different speeds of propagation.

Validation of Vehicle Driving Simulator from Perspective of Velocity and Trajectory Based Driving Behavior under Curve Conditions

With their advantages of high experimental safety, convenient setting of scenes, and easy extraction of control parameters, driving simulators play an increasingly important role in scientific research, such as in road traffic environment safety evaluation and driving behavior characteristics research. Meanwhile, the demand for the validation of driving simulators is increasing as its applications are promoted. In order to validate a driving simulator in a complex environment, curve road conditions with different radii are considered as experimental evaluation scenarios. To attain this, this paper analyzes the reliability and accuracy of the experimental vehicle speed of a driving simulator. Then, qualitative and quantitative analysis of the lateral deviation of the vehicle trajectory is carried out, applying the cosine similarity method. Furthermore, a data-driven method was adopted which takes the longitudinal displacement, lateral displacement, vehicle speed and steering wheel angle of the vehicle as inputs and the lateral offset as the output. Thus, a curve trajectory planning model, a more comprehensive and human-like operation, is established. Based on directional long short-term memory (Bi–LSTM) and a recurrent neural network (RNN), a multiple Bi–LSTM (Mul–Bi–LSTM) is proposed. The prediction performance of LSTM, MLP model and Mul–Bi–LSTM are compared in detail on the validation set and testing set. The results show that the Mul–Bi–LSTM model can generate a trajectory which is very similar to the driver’s curve driving and have a preferable generalization performance. Therefore, this method can solve problems which cannot be realized in real complex scenes in the simulator validation. Selecting the trajectory as the validation parameter can more comprehensively and intuitively reflect the simulator’s curve driving state. Using a speed model and trajectory model instead of a real car experiment can improve the efficiency of simulator validation and lay a foundation for the standardization of simulator validation.

Incidental exposure to hedonic and healthy food features affects food preferences one day later

Memories acquired incidentally from exposure to food information in the environment may often become active to later affect food preferences. Because conscious use of these memories is not requested or required, these incidental learning effects constitute a form of indirect memory. In an experiment using a novel food preference paradigm (n = 617), we found that brief incidental exposure to hedonic versus healthy food features indirectly affected food preferences a day later, explaining approximately 10% of the variance in preferences for tasty versus healthy foods. It follows that brief incidental exposure to food information can affect food preferences indirectly for at least a day. When hedonic and health exposure were each compared to a no-exposure baseline, a general effect of hedonic exposure emerged across individuals, whereas health exposure only affected food preferences for high-BMI individuals. This pattern suggests that focusing attention on hedonic food features engages common affective processes across the general population, whereas focusing attention on healthy food features engages eating restraint goals associated with high BMI. Additionally, incidental exposure to food features primarily changed preferences for infrequently consumed foods, having less impact on habitually consumed foods. These findings offer insight into how hedonic information in the obesogenic food environment contributes to unhealthy eating behavior that leads to overweight and obesity. These findings further motivate the development of interventions that counteract the effects of exposure to hedonic food information and that broaden the effects of exposure to healthy food information.

Cold-induced anesthesia impairs path integration memory in dung beetles

Path integration is a general mechanism used by many animals to maintain an updated record of their position in relation to a set reference point.1-11 To do this, they continually integrate direction and distance information into a memorized home vector. What remains unclear is how this vector is stored, maintained, and utilized for successful navigation. A recent computational model based on the neuronal circuitry of the insect central complex suggests that home vector memories are encoded across a set of putative memory neurons and maintained through ongoing recurrent neural activity.12 To better understand the nature of the home vector memory and experimentally assess underlying mechanisms for maintaining it, we performed a series of experiments on the path integrating dung beetle Scarabaeus galenus.13 We found that, while the directional component of the home vector was maintained for up to 1 h, the distance component of the vector memory decreased gradually over time. Using cold-induced anesthesia, we disrupted the neural activity of beetles that had stored a home vector of known length and direction. This treatment diminished both components of the home vector memory, but by different amounts-the homing beetles lost their distance memory before their directional memory. Together, these findings present new insights into the functional properties of home vector memories and provide the first empirical evidence that a biological process that can be disrupted by cold-induced anesthesia is essential to support homing by path integration.

Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems

Many recent research efforts have exploited data sparsity for the acceleration of convolutional neural network (CNN) inferences. However, the effects of data transfer between main memory and the CNN accelerator have been largely overlooked. In this work, the authors propose a CNN acceleration technique that leverages hardware/software co-design and exploits the sparsity in input feature maps (IFMs). On the software side, the authors' technique employs a novel lossless compression scheme for IFMs, which are sent to the hardware accelerator via direct memory access. On the hardware side, the authors' technique uses a CNN inference accelerator that performs convolutional layer operations with their compressed data format. With several design optimization techniques, the authors have implemented their technique in a field-programmable gate array (FPGA) system-on-chip platform and evaluated their technique for six different convolutional layers in SqueezeNet. Results reveal that the authors' technique improves the performance by 1.1×–22.6× while reducing energy consumption by 47.7%–97.4% as compared to the CPU-based execution. Furthermore, results indicate that the IFM size and transfer latency are reduced by 34.0%–85.2% and 4.4%–75.7%, respectively, compared to the case without data compression. In addition, the authors' hardware accelerator shows better performance per hardware resource with less than or comparable power consumption to the state-of-the-art FPGA-based designs.