Asynchronous Wrapper-Based Low-Power GALS Structural QDMA

Abstract

The design of System-on-Chip systems using synchronous circuits involves complex clock distribution strategies, which envisage challenges for designers to integrate large-scale systems. Globally Asynchronous Locally Synchronous architectures containing asynchronous port controllers encapsulated in the self-timed wrapper have been adopted in this work. These port controllers communicate through Asynchronous Finite State Machines defined by Signal Transition Graphs are implemented adopting the C element. This GALS architecture implemented for the point-to-point interface can also be modified for the multipoint interface. The proposed methodology uses a two-phase handshake protocol to communicate between two Locally Synchronous modules as it has fewer signal transitions, which, in turn, reduces latency. In this paper, the Queue Direct Memory Access subsystem is implemented using the Vivado simulator on UltraScale+™ device at a maximum frequency of 257.4MHz, and various parameters are reported. A comparison shows that the proposed wrapper has improved latency time of 53%, with a reduction in power dissipated by 27% and an increase in gate count by 13%.