A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration

Abstract

Low-cost high-volume internet of things sensors require an end-to-end secure private-content exchange. Restricted energy and computing of system-on-a-chip for low-cost sensor applications drive lightweight hardware acceleration of security primitives. A trade-off between power and time needs to be achieved to develop such primitives. The main challenge is to handle memory transportation in the crypto-accelerator. Here we propose different approaches for AES-128/256 Sbox acceleration schemes. We designed a Sbox unit to be connected as a logic unit. The unit was tested as a RISC-V ISA instruction in the RISC-V processor to reduce software execution times. This unit was also included in an AES hardware core with direct memory access (DMA), which avoids using the main processor to access the data. We fabricated a RISC-V based 32-bit SoC in a standard 180nm CMOS technology that includes the Sbox calculation using pipeline and a pure-combinational approach. Measurement results indicate lower memory access and lower energy requirements than pure software approaches up to 100 times with a custom Sbox instruction. The AES core also provides a minimum energy consumption of 3.58 pJ/cycle. At its best, the combined SoC performs the encryption in active-mode with energy consumption of 9.7 pJ/bit. This solution offers up to three times energy savings compared to previously reported work.